Mixed-Signal Switch Driver Biasing for Low-Distortion DAC Clocks
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Solution Overview
Problem
High-speed digital-to-analogue converters (DACs) face issues with third-order distortion due to currents flowing into and out of parasitic capacitances in differential switching circuits, and timing mismatches between analog segments and switch driver circuits, which are exacerbated by miniaturization and reduced supply voltages, leading to distortion and calibration challenges.
Innovation Solution
The implementation of a modified differential switching circuit with four FETs per output node and a modified switch driver circuit using time-interleaved clock signals and mask signals to control FETs in a repeating series of phases, and the use of NMOS data-controlled switches to ensure consistent clock signal delivery to output switches, reducing distortion and timing mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization and reduced supply voltages are used to increase integration density, then device size and power consumption are reduced, but timing mismatches and third-order distortion are exacerbated
Solution Approach 1:
The switching circuit is divided into multiple independent segments, each with its own differential switching circuitry. This segmentation allows each segment to be independently optimized and calibrated, reducing the cumulative timing mismatches that would occur in a monolithic design. The segmentation principle is applied by creating multiple parallel current source paths that can be individually controlled and matched.
Solution Approach 2:
The patent employs calibration techniques that dynamically adjust circuit parameters (such as switching timings and current levels) to compensate for manufacturing variations and miniaturization effects. By changing operational parameters through calibration circuits and procedures, the system achieves precise timing matching despite physical size reductions and voltage scaling.
2Speed
If conventional differential switching circuits are used in high-speed DACs, then conversion speed is achieved, but third-order distortion increases due to parasitic capacitances
Solution Approach 1:
The patent extracts and removes the sources of third-order distortion by eliminating parasitic capacitance paths. This is achieved through a novel switching architecture that avoids traditional differential switching configurations known to generate distortion. The harmful parasitic elements are taken out of the signal path through careful circuit topology design.
Solution Approach 2:
The patent converts potential harmful effects into beneficial ones by using calibration techniques that measure and compensate for remaining distortions. The calibration process transforms the harmful third-order distortion into a correctable parameter, turning a disadvantage into an opportunity for precision optimization through feedback and adjustment mechanisms.
3Measurement precision
If calibration procedures are implemented to reduce timing mismatches, then accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements calibration procedures that are performed during manufacturing or initialization before the device enters normal operation. By conducting calibration in advance, the system establishes precise timing relationships and compensates for variations upfront, eliminating the need for complex real-time calibration circuitry during operation.
Solution Approach 2:
The calibration system is designed to be self-contained and automated, requiring minimal external intervention. The calibration circuits automatically adjust timing and performance parameters without manual calibration, and the system self-compensates for variations through built-in reference circuits and feedback mechanisms, reducing the burden on manufacturing complexity.
Data Source
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AI summary
A switching circuit, comprising: a main switch (SW1) having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal (CK) thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage (VON) to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.