Cascode Output Driver for Wide-Range High-Voltage GPIO
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Solution Overview
Problem
Existing GPIO circuits face reliability degradation, increased static power consumption, and reduced operation speed when operating at high voltages due to overvoltage issues, particularly when using CMOSFETs with medium gate oxide films designed for lower voltages, making them unsuitable for high-speed and wide-range voltage applications.
Innovation Solution
A cascode structure using three PMOSFETs and three NMOSFETs connected between a voltage supply node and an output node, with dynamic gate control units generating pull-up and pull-down gate control voltages to manage voltage levels and prevent hot carrier injection, allowing for high voltage and wide-range voltage operations while maintaining transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOSFETs with medium gate oxide film for 1.8V operation are used in high voltage (3.3V) applications, then device destruction occurs due to overvoltage
Solution Approach 1:
The output driver is divided into multiple transistor stages (first output driver stage with PMOS transistors, second output driver stage with NMOS transistors) that sequentially handle different portions of the voltage swing. This segmentation allows each transistor to operate within its safe voltage range while the combined stages achieve high voltage output capability.
Solution Approach 2:
Intermediate voltage nodes (first intermediate node, second intermediate node) are introduced between the transistors to act as voltage mediators. These intermediate nodes progressively build up the voltage from the low voltage supply to the high voltage output level, preventing any single transistor from experiencing excessive voltage stress.
2Adaptability or versatility
If general purpose input/output (GPIO) circuit for high voltage is made using low voltage transistors, then reliability degradation occurs due to overvoltage
Solution Approach 1:
The gate control voltages are dynamically adjusted based on the operating conditions. The first gate control voltage is applied to the first PMOS transistor, and the second gate control voltage is applied to the second PMOS transistor, with these voltages changing during operation to optimize performance and protect against overvoltage conditions.
Solution Approach 2:
Different voltage parameters are used for different transistors in the same circuit. The first power supply voltage supplies the first output driver stage, while the second power supply voltage supplies the second output driver stage, with these voltages being different to match the specific requirements of each transistor stage.
3Adaptability or versatility
If high voltage operation is implemented with low voltage transistors, then static power consumption increases
Solution Approach 1:
The output driver operates in periodic phases where transistors are turned on and off in sequence. During high voltage output, only specific transistors conduct at different times, reducing the overall static power consumption compared to having all transistors continuously conducting.
4Adaptability or versatility
If high voltage operation is implemented with low voltage transistors, then operation speed degrades
Solution Approach 1:
Gate control voltages are prepared and applied in advance to the transistors before the actual switching operation. This preliminary action ensures that transistors are ready to switch quickly when needed, maintaining high operation speed even in high voltage mode.
Data Source
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Figure 3~4
AI summary
An output driver and a data output driving circuit using the output driver includes a pull-up driver (10) including at least three pull-up transistors (PM1-PM3) connected between a high voltage (OVDD) and an output node (NO1) in a stack structure of three stages or more and a pull-down driver (20) including at least three pull-down transistors (NM1-NM3) connected between a ground node and the output node (NO1) in a stack structure of three stages or more.