Gate Electrode Segmentation for Nanosheet Void Prevention
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Solution Overview
Problem
The formation of voids between channel regions in semiconductor devices during the fabrication process leads to performance deterioration, as existing technologies struggle to effectively fill the spaces between nanosheets without creating incompletely filled areas, which can result in reduced integration and efficiency.
Innovation Solution
A semiconductor device design featuring a gate electrode with a length greater than the spacing between nanosheets, ensuring complete filling of the space between nanosheets before filling the space between spacers, and utilizing a gate insulating layer with different permittivity layers to enhance performance and prevent void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode length is increased to fill the space between nanosheets, then void formation is prevented, but device complexity increases
Solution Approach 1:
The gate electrode is divided into two distinct regions: a first region with a first stack structure and a second region with a second stack structure. This segmentation allows each region to be optimized independently for its specific function, preventing void formation while managing device complexity through modular design.
Solution Approach 2:
Different stack structures are applied to different regions of the gate electrode based on local requirements. The first region has a configuration optimized for filling spaces between nanosheets, while the second region has a configuration optimized for surrounding and controlling the channel, ensuring each area has the appropriate structure for its purpose.
2Reliability
If the gate electrode completely surrounds the nanosheets, then channel control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is segmented into a first region that fills between nanosheets and a second region that surrounds them, allowing independent formation and optimization of each region's positioning and dimensions, thereby reducing overall manufacturing precision requirements.
Solution Approach 2:
The gate electrode structure is formed in a predetermined sequence where the first region is established to fill spaces between nanosheets before the second region is formed to surround them, ensuring proper positioning and control is achieved through controlled fabrication steps.
Data Source
AI summary
A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.