Vertical Transistor Structure for Semiconductor Memory Integration
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase data storage capacity while minimizing space and reducing power consumption, which is limited by the planar type transistor structure, and to accurately form the drain region in vertical transistors for improved integration and reliability.
Innovation Solution
A semiconductor memory device with a vertical transistor structure that includes a buried bit line junction region, an etch stop film, and interlayer dielectric films with different etch selectivities, allowing for increased channel width and reduced gate resistance by expanding the gate's contact area with the active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar type transistor structure is used, then device integration is simplified, but data storage capacity is limited and power consumption increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure, changing the current flow direction from lateral to vertical. This dimensional change allows the bit line to extend deeper into the substrate, increasing the effective channel area and thus the data storage capacity without proportionally increasing power consumption
2Productivity
If vertical transistor structure is adopted to increase integration, then data storage capacity improves, but forming the drain region accurately becomes difficult
Solution Approach 1:
The patent forms the drain region at a predetermined depth below the semiconductor substrate surface before forming the vertical channel. This preliminary positioning of the drain region provides a reliable reference point for subsequent vertical etching processes, ensuring accurate alignment and positioning of the vertical transistor structure
Solution Approach 2:
The patent introduces a sacrificial layer between the drain region and the vertical channel structure. This sacrificial layer acts as an intermediary that facilitates precise positioning of the vertical channel relative to the drain region, and is later removed to create the final vertical transistor structure with accurate geometric relationships
3Reliability
If channel width is increased to reduce gate resistance, then contact resistance characteristics improve, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by extending the bit line depth into the substrate, thereby increasing the effective channel area in the vertical direction. This allows the channel width to be effectively increased for reduced gate resistance without proportionally increasing the lateral device footprint, as the additional channel area is achieved through deeper vertical extension rather than wider lateral spread
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the contact resistance characteristics, stability, and reliability of the semiconductor device by increasing the channel width and reducing the gate resistance, thereby improving data storage capacity and power efficiency.
Implementation Method 1
an etch stop film disposed on an exposed surface of the buried bit line; an etch stop film disposed on an exposed surface of the buried bit line
Implementation Method 2
interlayer dielectric films with different etch selectivities
Data Source
AI summary
A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.