Multi-layer Fin Structure for Threshold Voltage Uniformity
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Solution Overview
Problem
Advanced integrated circuits with small feature sizes, such as FinFETs, face issues like non-uniform threshold voltage distribution and current crowding due to high aspect ratios and non-uniform fin widths, leading to degraded device performance.
Innovation Solution
A semiconductor structure and method involving a multi-layer fin structure with epitaxially grown layers of different compositions and heights, where the fin layers have varying germanium concentrations to improve threshold voltage uniformity and current density, achieved through processes like CVD and ALD, without increasing process cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If narrow fin width is used for short channel control, then FinFET device performance is enhanced, but non-uniform distribution of threshold voltage occurs due to MG or S/D profile design and dimension effect
Solution Approach 1:
The patent applies local quality by creating a multi-layer fin structure where different regions of the fin have different material compositions and doping concentrations. Specifically, the fin structure includes a first region with a first doping concentration and a second region with a second doping concentration, allowing local optimization of electrical properties to achieve uniform threshold voltage distribution while maintaining narrow fin width for short channel control.
Solution Approach 2:
The fin structure is segmented into multiple layers with different materials and doping profiles. The multi-layer fin structure divides the fin into distinct regions (first region and second region) with varying germanium concentrations and doping levels, enabling independent optimization of each segment's electrical characteristics to resolve the threshold voltage uniformity issue.
2Manufacturing precision
If multi-layer fin structure with varying germanium concentrations is used, then threshold voltage uniformity is improved, but device structure complexity increases
Solution Approach 1:
The patent employs composite materials by creating a multi-layer fin structure composed of different semiconductor materials with varying germanium concentrations. The fin structure integrates silicon-germanium layers with different Ge percentages (e.g., first region with higher Ge concentration, second region with lower Ge concentration) to achieve uniform threshold voltage while managing structural complexity through systematic material composition design.
3Manufacturing precision
If epitaxial growth processes are used to form multi-layer fin structure, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent utilizes parameter changes during epitaxial growth to achieve precise control over fin layer composition. By varying growth parameters such as temperature, pressure, and precursor flow rates during different stages of epitaxial growth, the process forms multi-layer fin structures with controlled germanium concentrations and doping profiles, improving manufacturing precision while managing process complexity through systematic parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances device performance by improving threshold voltage uniformity, increasing current density, and reducing drain-induced barrier lowering, while maintaining DC gain without AC penalty and avoiding bottom off current and voltage shift penalties.
Implementation Method 1
forming a first fin layer on a semiconductor substrate, wherein the first fin layer includes silicon germanium having a first concentration of germanium; forming a second fin layer over the first fin layer, wherein the second fin layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium
Implementation Method 2
achieved through processes like CVD and ALD
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.