Solid State Power Controller Current Sharing via Isolated FET Sources
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Solution Overview
Problem
In high voltage aircraft applications, solid state power controllers (SSPCs) face challenges with uneven current distribution among parallel MOSFETs during inductive load switching off, leading to thermal imbalance and increased risk of FET destruction due to variations in gate threshold voltage and temperature, which necessitates high safety margins and is not addressable by existing mechanisms.
Innovation Solution
The source potentials of lower-end FETs are isolated to function as adjustable source resistors, implementing feedback resistors between each FET's source and load output to optimize current distribution, using reverse FETs in the third quadrant mode to provide current feedback and reduce gate voltage proportionally with current, creating discrete sources connected via high impedance resistors to enable even current sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple MOSFETs are connected in parallel to increase current carrying capability, then the current carrying capability increases, but uneven current distribution occurs among the FETs
Solution Approach 1:
The patent introduces individual source resistors for each MOSFET in the parallel configuration. These resistors create local voltage drops that provide negative feedback, ensuring each FET operates at its maximum safe power dissipation level. This local quality adjustment compensates for variations in FET characteristics and ensures uniform current distribution across all parallel devices.
Solution Approach 2:
The source resistors implement a feedback mechanism where the voltage drop across each resistor is proportional to the current through that FET. This feedback signal naturally limits the current through each device to its maximum safe operating level, preventing any single FET from carrying excessive current and ensuring balanced current sharing among all parallel FETs.
2Use of energy by moving object
If FETs operate in linear mode to absorb inductive energy, then inductive energy can be absorbed, but thermal imbalance occurs due to uneven current sharing
Solution Approach 1:
During linear mode operation for inductive energy absorption, each FET experiences different current levels due to threshold voltage variations. The individual source resistors create localized voltage drops that provide negative feedback, ensuring each FET dissipates power within its safe operating limits. This prevents thermal imbalance even though all FETs are operating in linear mode simultaneously.
Solution Approach 2:
The source resistors implement feedback control during linear mode by creating voltage drops proportional to each FET's current. This feedback mechanism naturally limits the current through each device to its maximum safe power dissipation level, preventing thermal runaway and ensuring uniform temperature rise across all parallel FETs during inductive energy absorption.
3Reliability
If high safety margins are designed into the SSPC to prevent FET destruction, then reliability improves, but power dissipation and voltage drop increase
Solution Approach 1:
The patent changes the operating parameters by introducing source resistors that dynamically adjust the effective on-resistance of each FET branch. Instead of designing for worst-case scenarios with uniform high safety margins, the source resistors enable each FET to operate close to its maximum safe power dissipation level by providing individualized current limiting, thereby reducing overall power losses while maintaining high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures more even current distribution among FETs during inductive load switching off, reducing the risk of thermal imbalance and FET destruction, thereby enhancing the reliability and efficiency of SSPCs in high voltage applications.
Implementation Method 1
The source potentials of lower-end FETs are isolated to function as adjustable source resistors, implementing feedback resistors between each FET's source and load output
Implementation Method 2
creating discrete sources connected via high impedance resistors to enable even current sharing
Data Source
Figure 1
Figure 2
AI summary
A solid state power controller comprising: a plurality of pairs of FETs M1-M6 connected in parallel, each pair comprising a first, forward-facing FET, M1, M2, M6 and a second, backward-facing FET M3-M5 connected by their respective sources; gate drive means for switching said FETs on and off; and means R2-R5 for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3rd quadrant operation mode.