Negative-Capacitance FET Fabrication with Ferroelectric Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving low subthreshold swing (SS) for low power consumption, particularly in Internet of Things (IoT) applications, due to difficulties in incorporating ferroelectric materials into existing CMOS processing, leading to defects, high leakage, and voltage hysteresis, as well as mismatched capacitance across different device dimensions.
Innovation Solution
A method for fabricating negative-capacitance field-effect transistors (NC-FETs) using existing CMOS processing, involving the formation of a gate stack with a ferroelectric layer and metal gate electrodes, while maintaining drive current performance and matching capacitance between the ferroelectric and CMOS materials, allowing for tunable negative capacitance and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric material is incorporated into gate-first CMOS processing, then negative capacitance is achieved, but high thermal budget causes defects, high leakage and voltage hysteresis
Solution Approach 1:
The fabrication process is divided into two distinct sequences: gate-first (forming gate, then FE layer) and gate-last (forming FE layer, then gate). This segmentation allows selection of the appropriate process based on thermal budget constraints, with gate-last being preferred to avoid high-temperature damage to the FE material.
Solution Approach 2:
The conventional gate-first approach is inverted to gate-last processing, where the ferroelectric layer is formed first and the gate electrode is added afterward. This inversion protects the FE material from high-temperature processing that would otherwise damage it.
2Temperature
If ferroelectric material is incorporated into gate-last CMOS processing, then thermal damage is avoided, but filling two gate stacks in short gate length trench is difficult
Solution Approach 1:
The gate electrode is formed in advance as part of the gate stack structure before the ferroelectric layer is deposited. This preliminary action ensures proper alignment and makes subsequent FE layer formation straightforward, avoiding the difficulty of filling short trenches afterward.
3Length of moving object
If gate length changes, then device scaling is achieved, but capacitance balance between FE/gate oxide and Si substrate is lost
Solution Approach 1:
The thickness of the ferroelectric layer is adjusted as a variable parameter to compensate for changes in gate length and device width. By tuning the FE layer thickness, the capacitance balance is maintained across different device dimensions, ensuring proper NC-FET operation for both single gate and extended/double gate configurations.
4Area of moving object
If device width changes, then design flexibility is achieved, but capacitance balance changes and negative capacitance operation is compromised
Solution Approach 1:
The ferroelectric layer thickness is adjusted according to device width variations to maintain capacitance balance. This parameter adjustment ensures that both single gate and extended/double gate FETs achieve proper negative capacitance operation across different width dimensions.
5Device complexity
If conventional structures are used for NC-FET, then fabrication is simplified, but hysteresis-free operation is difficult to achieve across various W/L scaling
Solution Approach 1:
The thickness of the ferroelectric layer is optimized and adjusted based on device dimensions to achieve hysteresis-free operation. By carefully controlling the FE layer thickness parameter, the patent enables reliable NC-FET operation across various W/L scaling without requiring complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables the production of NC-FETs with reduced subthreshold swing and maintained drive current performance, achieving capacitance matching across various device dimensions, thereby addressing the challenges of defects, leakage, and hysteresis, and ensuring proper operation across all length and width dimensions.
Implementation Method 1
A negative-capacitance (NC) in nanoscale devices have been previously developed to provide voltage amplification for low power nanoscale devices
Implementation Method 2
NC MOSFETs (NC-FETs) have been recently developed which utilizes a ferroelectric (FE) material to achieve negative capacitance and modulate gate voltage
Implementation Method 3
forming a gate oxide over the semiconductor substrate
Data Source
AI summary
Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.