OTP Memory Cell Voltage Stress Management
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Solution Overview
Problem
Conventional one-time programming (OTP) non-volatile memory cells face challenges in operating efficiently at low voltage conditions, leading to high energy consumption and potential transistor burnout due to excessive voltage stress during programming cycles.
Innovation Solution
The design incorporates a floating gate transistor, an isolation transistor, and a select transistor, fabricated using a medium voltage device process for the floating gate and low voltage device processes for the isolation and select transistors, with optimized gate oxide layers and well regions to manage voltage stress, allowing for low voltage operation without transistor burnout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional OTP memory cell structure is used, then manufacturing compatibility with standard CMOS process is achieved, but voltage stress during programming causes transistor burnout and high energy consumption
Solution Approach 1:
The memory cell is segmented into three distinct transistor components: floating gate transistor, isolation transistor, and select transistor. This segmentation allows each transistor to be optimized for specific voltage stress conditions, with the isolation transistor protecting the floating gate transistor from excessive voltage during programming operations
Solution Approach 2:
The isolation transistor serves as an intermediary component between the floating gate transistor and the bit line. It mediates the voltage stress by being positioned in the voltage path during programming, absorbing excessive voltage stress and preventing it from reaching the floating gate transistor, thereby reducing energy consumption and preventing burnout
2Adaptability or versatility
If medium voltage device process is used for all transistors, then programming capability is achieved, but voltage stress exceeds transistor withstand limits causing burnout
Solution Approach 1:
Different transistor regions are assigned different voltage stress tolerances and operational characteristics. The floating gate transistor is designed for low voltage operation with high sensitivity, while the isolation transistor is designed to withstand medium voltage stress during programming. This local differentiation of quality allows the cell to achieve programming capability while protecting sensitive components from excessive voltage stress
Solution Approach 2:
The isolation transistor is positioned in advance in the voltage path to provide cushioning protection. During programming operations, it absorbs excessive voltage stress before it can reach the floating gate transistor, preventing burnout and ensuring reliable operation
3Ease of manufacture
If floating gate transistor with single gate structure is used, then manufacturing process compatibility is improved, but voltage control during programming becomes less precise
Solution Approach 1:
The isolation transistor acts as an intermediary that enables precise voltage control of the floating gate transistor. By controlling the isolation transistor's gate voltage, the voltage applied to the floating gate transistor can be precisely regulated during programming operations, maintaining manufacturing precision while using a simpler single-gate structure
Data Source
AI summary
A one time programming non-volatile memory cell includes a first floating gate transistor with a single gate structure, an isolation transistor, and a select transistor. A first terminal of the first floating gate transistor is connected with a second control line. A floating gate of the first floating gate transistor is in a floating state. A first terminal of the isolation transistor is connected with a second terminal of the first floating gate transistor. An isolation gate of the isolation transistor is connected with an isolation line. A first terminal of the select transistor is connected with a second terminal of the isolation transistor. A second terminal of the select transistor is connected with a first control line. A select transistor of the select transistor is connected with a word line.