On-Grid Dummy Poly Layout for CMP Anti-Dishing at 5 Nm
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Solution Overview
Problem
Integrated circuit layouts face constraints due to design rules that require significant spacing between active and dummy device structures, leading to inefficient use of chip area and challenges in preventing dishing during chemical mechanical polishing (CMP), particularly at the 5 nm technology node.
Innovation Solution
The method involves generating an integrated circuit layout with a first array of linear features over active device areas and inserting a second array of linear features as dummy fill, which are on the same grid as the first array, allowing the dummy fill to be closer to the active device area, thereby improving anti-dishing performance and reducing empty space on the chip. This is achieved by forming a continuous array of poly lines on the semiconductor substrate, with the dummy device structure extending over a substantial portion of the distance between active device areas, utilizing the same line spacing and width as the active device features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If significant spacing is provided between active and dummy device structures according to design rules, then proper electrical isolation and manufacturability are ensured, but chip area efficiency deteriorates and dishing mitigation becomes challenging
Solution Approach 1:
The patent merges the active device structure array with the dummy device structure array into a single continuous poly line structure. By making the dummy fill on-grid with the active device features and spacing them by only one line spacing, the structure combines both functional and dummy regions into one continuous formation, eliminating the need for separate spacing and achieving both electrical isolation through the isolation structure and efficient area utilization.
Solution Approach 2:
The patent applies local quality by having the dummy fill structures match the specific geometric properties (line width, line spacing, pitch) of the active device features locally. This local matching allows the dummy structures to be on-grid with active devices and spaced by minimal distance while still providing adequate dishing mitigation in their local region without requiring global spacing increases.
2Reliability
If significant spacing is provided between active and dummy device structures, then design rule compliance is achieved, but anti-dishing performance deteriorates
Solution Approach 1:
The patent combines the dummy fill structures with the active device structures into a single continuous poly line formation. This merging allows the dummy structures to be positioned much closer (only one line spacing away) while still being formed in the same continuous process step, achieving both design rule compliance and superior anti-dishing performance through the continuous structure's presence during CMP.
Solution Approach 2:
The patent places the dummy fill structures in advance as part of the continuous poly line formation before any subsequent processing steps. By pre-positioning these dummy structures on-grid and spaced by minimal distance, they are already in place to provide dishing mitigation during the CMP process that follows, ensuring manufacturing precision is maintained throughout the fabrication sequence.
3Area of stationary object
If dummy device structures are placed closer to active device areas, then chip area efficiency improves, but design rule violations occur
Solution Approach 1:
The patent merges the dummy fill with the active device structures into one continuous poly line structure that is formed in a single patterning and etching process. This merging allows the structures to be placed as close as one line spacing without violating design rules, because the continuous formation process ensures uniformity and the isolation structure provides the necessary electrical separation, thereby achieving maximum chip area efficiency while maintaining compliance.
4Area of stationary object
If dummy device structures are placed closer to active device areas, then empty space reduction is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the dummy fill placement with the active device structure formation into a single continuous poly line definition process. By making both structures on-grid with the same pitch and forming them continuously, the layout complexity is actually reduced compared to treating them separately, while achieving maximum empty space reduction through minimal spacing of one line spacing between active and dummy regions.
Data Source
AI summary
An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.