Stacked CMOS Transistor Structure for Contact Area and Gate Control
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Solution Overview
Problem
Current semiconductor device fabrication technologies face challenges in achieving optimal performance and scaling for stacked transistors, particularly in providing increased source/drain contact area and reduced distance between the source/drain contact and the channel, while maintaining effective electrostatic control and channel mobility for both nFETs and pFETs.
Innovation Solution
The development of a stacked semiconductor device with a lower transistor featuring a fin channel and a vertically stacked upper transistor with a diamond-shaped nano channel, where the upper transistor's gate structure wraps around the nano channel, enhancing contact area and reducing the distance between source/drain regions and the channel, and utilizing epitaxial growth of SiGe layers for improved electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar transistor structures are used, then manufacturing is simpler, but source/drain contact area is insufficient and distance between contacts and channel is too large
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional vertically stacked transistor structures. The upper and lower transistors are stacked vertically, with the upper transistor positioned directly above the lower transistor, enabling increased source/drain contact area while maintaining compact footprint. This vertical stacking allows simultaneous contact with multiple channels (fin channels and diamond-shaped nano channels) from the same source/drain regions.
2Area of moving object
If vertically stacked transistor structure is used, then source/drain contact area increases, but electrostatic control becomes more challenging
Solution Approach 1:
The gate structures are positioned to wrap around and contact the channels in a nested configuration. The lower gate structure contacts the fin channel sidewalls, while the upper gate structure wraps around the diamond-shaped nano channel. This nested gate arrangement provides comprehensive electrostatic control over the channels, with gates positioned adjacent to and surrounding the channel regions, enabling effective field effect control despite the vertical stacking.
3Productivity
If distance between source/drain contacts and channel is reduced, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into distinct upper and lower transistor regions, each with its own channel structure (diamond-shaped nano channel and fin channel respectively). The source/drain regions are segmented to provide separate contact areas for each transistor type. This segmentation allows independent optimization of each transistor's geometry and positioning, facilitating precise alignment while maintaining reduced distances between contacts and channels.
4Reliability
If different channel structures (fin and diamond-shaped) are used for nFET and pFET, then channel mobility is optimized, but device complexity increases
Solution Approach 1:
Different channel structures are assigned to specific transistor types based on their optimal performance characteristics. The lower transistor features fin channels optimized for one transistor type (e.g., nFET), while the upper transistor features diamond-shaped nano channels optimized for the other type (e.g., pFET). This local optimization of channel geometry allows each transistor to achieve maximum channel mobility for its specific type, with the fin structure providing good electrostatic control for one polarity and the diamond-shaped structure providing superior mobility for the other polarity.
Data Source
AI summary
A stacked semiconductor device includes stacked transistors. A lower transistor may be a p-type FinFET and an upper transistor vertically above the lower transistor may be a n-type nanostructure FET. The lower transistor may include a fin channel with a (110) orientated crystalline side surface. End surfaces of the fin channel contact a respective lower source/drain (S/D) region. The (110) orientated crystalline side surface may contact a lower gate structure. The upper transistor includes a diamond-shaped nano channel with a (111) orientated crystalline perimeter surface. End surfaces of the diamond-shaped nano channel may contact a respective upper S/D region. An upper gate structure may wrap around and contact the (111) orientated crystalline perimeter surface. An electrical isolation structure may separate the upper transistor from the lower transistor.