NMOS Gate Driver Adaptive Blanking via Miller Plateau Detection
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Solution Overview
Problem
Existing gate driver integrated circuits face challenges in setting a fixed blanking time that is both long enough to cover normal switch-on slewing time and short enough to prevent excessive heat generation in case of a short circuit, as a fixed blanking time may fail to distinguish between normal switching and actual short circuit conditions effectively.
Innovation Solution
Implementing an adaptive blanking time based on the detection of the Miller plateau in the gate voltage during the transistor's switching-on phase, which masks the short circuit detection circuitry until the end of the Miller plateau, ensuring accurate differentiation between normal slewing and short circuit conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed blanking time is used to mask short circuit detection, then normal switch-on slewing is covered, but excessive heat generation occurs during actual short circuits due to delayed detection
Solution Approach 1:
The patent transitions from a fixed blanking time to a dynamic adaptive blanking time that adjusts based on the detected Miller plateau duration. The masking period is extended only as long as necessary to cover the actual switching event, then automatically reduced to enable timely short circuit detection, resolving the contradiction between covering normal slewing and enabling timely protection.
Solution Approach 2:
The patent changes the blanking time parameter from a static fixed value to a dynamic value that adapts based on the Miller plateau detection. By monitoring the gate voltage plateau characteristics and adjusting the masking duration accordingly, the system optimizes the balance between false alarm prevention and short circuit protection responsiveness.
2Loss of time
If a long fixed blanking time is used, then normal switching operations are covered, but short circuit detection is delayed causing device damage
Solution Approach 1:
The system dynamically adjusts the blanking time duration based on real-time detection of the Miller plateau in the gate voltage. During normal switching, the blanking time extends through the plateau to prevent false alarms. During short circuits, the plateau is absent or abnormal, causing the blanking time to expire sooner and enable rapid protection response.
Solution Approach 2:
The patent implements feedback by continuously monitoring the gate voltage characteristics during the blanking period. The detection circuitry observes whether the expected Miller plateau occurs and its duration, using this feedback to determine when to terminate the masking period, thereby adapting the response time based on actual switching behavior.
3Ease of operation
If masking is applied during the entire switching phase, then normal operations are protected from false alarms, but actual short circuits are not detected in time
Solution Approach 1:
The masking is applied dynamically only for the duration of the detected Miller plateau rather than for a fixed extended period. This adaptive approach maintains protection during normal switching operations while automatically reducing masking duration when short circuit conditions prevent the formation of a normal plateau, enabling timely detection and protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adaptive blanking time significantly reduces heat generation during potential short circuits by ensuring timely detection and response to actual short circuit conditions, while avoiding false alarms during normal switching operations.
Implementation Method 1
The comparator receives the drain voltage of the external NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply
Implementation Method 2
The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor
Implementation Method 3
The gate driver output drives the gate of the external NMOS transistor
Data Source
AI summary
A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau.