High-k Metal Gate Transistor Cover Layer Thickness

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Solution Overview

Problem

Aluminum diffusion through the sidewall of gate trenches in semiconductor devices affects the reliability and performance by degrading carrier mobility and increasing the likelihood of aluminum diffusion downward, leading to issues like time-dependent dielectric breakdown and bias temperature instability.

Innovation Solution

A method involving the formation of a cover layer with greater thickness at the corners of the gate trench bottom than in the middle region, achieved through magnetron sputtering or atomic layer deposition, inhibits aluminum diffusion and enhances device reliability and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a uniform cover layer is formed over the high-k dielectric layer, then the manufacturing process is simple, but aluminum diffuses through the sidewall of the gate trench, degrading device reliability and performance

Engineering Contradiction:
Improvedevice reliabilityVSAvoidcover layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating a cover layer with non-uniform thickness, specifically thicker at the corners of the gate trench bottom and thinner in the middle region. This localized thickness variation provides enhanced aluminum diffusion barrier precisely where the bow-shaped NWF metal layer creates maximum stress and diffusion risk at the corners, while maintaining adequate protection overall without unnecessarily complicating the entire structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If the cover layer is made uniformly thick, then manufacturing is easier, but aluminum diffusion through the gate trench sidewall degrades carrier mobility and increases dielectric breakdown risk

Engineering Contradiction:
Improveresistance to aluminum diffusionVSAvoidcover layer formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The cover layer is engineered with locally optimized thickness: thicker regions at the corners where aluminum diffusion is most problematic due to the bow-shaped NWF metal layer configuration, and thinner regions in the middle where diffusion risk is lower. This localized differentiation enhances aluminum diffusion resistance at critical locations while maintaining manufacturing feasibility through controlled deposition processes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces aluminum diffusion, improving the reliability and performance of semiconductor devices by creating a thicker cover layer at the corners of the gate trench, which prevents downward aluminum migration and enhances metal gate filling capacity.

Implementation Method 1

The cover layer is formed by forming the cover layer on the high-k dielectric layer, and sputtering the cover layer by magnetron sputtering, thereby causing the cover layer to have a thickness that is greater at the corners of the bottom of the gate trench than in the middle region of the bottom of the gate trench.

Methodology Applied
Scientific EffectMagnetron sputtering: Sputtering

Implementation Method 2

The cover layer is relatively thick at the bottom corners of the gate trench, which inhibits the diffusion of aluminum in the metal gate electrode

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9570611B2Method and device for high k metal gate transistors
Publication Date: 2017.02.14 SEMICON MFG INT (SHANGHAI) CORP
  • US9570611B2 patent drawing
  • US9570611B2 patent drawing
  • US9570611B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a dummy gate structure formed thereon and an offset spacer formed on a sidewall of the dummy gate structure. The method further includes removing the dummy gate structure to form a gate trench, forming a high-k dielectric layer on the bottom and the sidewall of the gate trench, and forming a cover layer over the high-k dielectric layer. The cover layer has a thickness that is greater at the corners of the bottom of the gate trench than in the middle region of the bottom of the gate trench.