DRAM Bit Line Contact Formation With Epitaxial Through-Hole Rebuild
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Solution Overview
Problem
The performance of dynamic random access memory (DRAM) is hindered by damage to bit line contact layers and the presence of non-volatile impurities during the etching process of pseudo bit line structures, which affects the operating speed of the memory.
Innovation Solution
A method is introduced where pseudo bit line structures are formed in through holes defined by pseudo bit line contact layers and sacrificial layers, and after removal, bit line contact layers are formed within these holes using epitaxial growth technology to avoid damage and impurities, thereby improving memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching process is used to remove pseudo bit line structures, then the pseudo bit line structures can be removed to form through holes, but the bit line contact layers are damaged and non-volatile impurities remain
Solution Approach 1:
The patent segments the bit line contact structure into two distinct parts: pseudo bit line contact layers (used temporarily during manufacturing) and actual bit line contact layers (formed later). This segmentation allows the pseudo structures to be removed without damaging the final contact layers, as they are formed at different stages and locations. The pseudo contact layers serve as placeholders that guide the subsequent formation of the real contact layers through the same through-holes.
Solution Approach 2:
The patent performs preliminary actions by first forming the pseudo bit line contact layers and pseudo bit line structures before the actual bit line contact layers. These preliminary structures define the through-holes and contact positions in advance, ensuring that when the real contact layers are formed, they automatically align correctly without requiring additional alignment steps or risking damage to existing contacts.
2Quantity of substance
If process node size is reduced continuously, then the memory density increases, but the performance of the memory deteriorates
Solution Approach 1:
The patent applies local quality by ensuring that the bit line contact layers have optimal local properties (high purity, correct crystalline structure, appropriate resistance) at the specific contact points with active areas, while the overall memory structure maintains high density through miniaturization. The selective formation process ensures that contact quality is optimized locally without compromising the global density improvement from process scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to bit line contact layers and residual impurities, enhancing the operating speed and performance of the memory by reducing resistance and ensuring accurate conductivity.
Implementation Method 1
bit line contact layers are formed within these holes using epitaxial growth technology
Data Source
AI summary
A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.