Local Interconnects for Semiconductor Device Density
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Solution Overview
Problem
As semiconductor device sizes decrease to increase device density, the aspect ratio of via openings increases, leading to higher contact resistance and reduced fabrication yields in conventional dual damascene interconnect structures, making it difficult to maintain electrical properties and reliability.
Innovation Solution
A semiconductor device with local interconnects featuring collinear gate line structures and conductive lines connecting source/drain regions, providing a larger contact area and lower contact resistance compared to conventional plugs, while simplifying the formation process and achieving high transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then device density increases, but aspect ratio of via openings increases leading to higher contact resistance
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: shallow trenches connecting adjacent source/drain regions within the same active area, and deeper vias connecting source/drain regions between different active areas. This segmentation allows each component to be optimized independently - shallow trenches have lower aspect ratios for reduced contact resistance, while deeper vias are minimized in number. The conductive lines are also segmented to connect only adjacent transistors rather than all transistors, reducing overall via count and contact resistance.
Solution Approach 2:
The patent applies different structural qualities to different locations in the interconnect network. Shallow trenches are used locally within active areas where low contact resistance is critical, while deeper vias are used only where necessary for inter-area connections. The conductive lines are configured to provide local interconnects only between adjacent transistors, creating a hierarchical quality distribution that optimizes contact resistance where it matters most while maintaining overall connectivity.
2Quantity of substance
If device size is reduced to increase device density, then device density increases, but fabrication yield decreases
Solution Approach 1:
The patent segments the interconnect formation into separate process steps for shallow trenches and deeper vias, allowing each to be optimized for its specific dimensional requirements. The shallow trenches can be formed with less aggressive etching parameters suitable for high-density layouts, while vias use optimized parameters for their deeper profiles. This segmentation improves fabrication yield by avoiding the need to use a single process regime for all interconnect features.
Solution Approach 2:
Instead of the conventional approach of forming all vias first then filling with metal, the patent inverts the sequence by first forming shallow trenches and filling them with conductive material, then forming deeper vias through the existing structure. This inverted sequence allows better control over the filling process and reduces defects, improving fabrication yield while supporting higher device density.
3Ease of manufacture
If conventional dual damascene process is used, then interconnect structure is formed, but contact resistance increases with higher aspect ratio
Solution Approach 1:
The patent divides the dual damascene process into separate operations for shallow trenches and deeper vias. The shallow trenches are formed and filled first with conductive material, creating low-contact-resistance local interconnects. Then deeper vias are formed through the structure and filled separately. This segmentation allows each etch and fill operation to be optimized for its specific aspect ratio, maintaining ease of manufacture while reducing overall contact resistance.
Solution Approach 2:
The patent transitions from a single vertical via dimension to a two-dimensional interconnect system incorporating both shallow horizontal trenches and deeper vertical vias. This dimensional change allows current to flow through lower-resistance shallow trench paths for local connections, reducing contact resistance while maintaining the manufacturability of the dual damascene process through systematic extension to multiple trench depths.
Data Source
AI summary
A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions.