Field Effect Transistor Gate Layout for Higher Surface Breakdown
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Solution Overview
Problem
High voltage field effect transistors often suffer from surface breakdown voltage due to complex extended low doped drain (LDD) structures, which increase process complexity and cost.
Innovation Solution
The implementation of a semiconductor structure with shallow trench isolation and dielectric gate spacers that surround field effect transistors, featuring a gate electrode with four sides and offset spacers on two sides, reduces the gate fringe area and improves surface breakdown characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the complex extended LDD structure from the device design. Instead of using the traditional complex LDD structure, the invention employs a simplified structure with standard spacers and gate electrode configuration, eliminating unnecessary complexity while maintaining surface breakdown characteristics through the shallow trench isolation and gate electrode design.
Solution Approach 2:
The patent applies local quality by modifying specific regions rather than the entire structure. The shallow trench isolation structure is implemented locally at the surface region, and the gate electrode is positioned specifically over the channel region, providing enhanced surface breakdown characteristics only where needed without requiring complex LDD structures throughout the device.
2Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the complex extended LDD structure that increases manufacturing cost. The simplified structure using standard spacers and gate electrode configuration reduces the number of fabrication steps and materials required, thereby lowering manufacturing cost while maintaining reliability through alternative design approaches.
Solution Approach 2:
The shallow trench isolation structure and gate electrode configuration serve multiple functions simultaneously: they provide surface breakdown protection, define the active region, and control the electrical characteristics. This multi-functionality eliminates the need for separate complex LDD structures, reducing manufacturing complexity and cost.
3Reliability
If gate fringe area is reduced through simplified structure, then surface breakdown voltage is enhanced, but device area may be constrained
Solution Approach 1:
The patent segments the device into distinct functional regions: the shallow trench isolation structure defines the active region boundaries, the gate electrode covers the channel region, and spacers are positioned at specific locations. This segmentation allows optimization of the gate fringe area in inter-gate regions without compromising the overall device area, as each segment serves its specific function efficiently.
Data Source
AI summary
A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.