Nanosheet Gate Isolation Using Backside Trenches and Self-Alignment
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Solution Overview
Problem
The challenge in integrated circuits is to effectively isolate gate electrodes of nanosheet transistors to prevent electrical shorting, which is difficult with conventional methods, especially when trying to increase computing power by increasing transistor density.
Innovation Solution
The use of backside trenches etched through the substrate and gate metals to electrically isolate individual gate electrodes of nanosheet transistors, allowing for self-aligned processing without separate photolithography, enabling higher density and better isolation capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate isolation methods are used, then manufacturing process is simpler, but gate electrodes cannot be effectively isolated leading to electrical shorting
Solution Approach 1:
The patent introduces backside trenches that extend from the front surface through the substrate to the back surface, creating a three-dimensional isolation structure. This vertical dimension allows the isolation structure to pass through the gate metal layer and electrically isolate adjacent gate electrodes without requiring complex lateral isolation structures at the gate level.
Solution Approach 2:
The isolation structure is segmented into multiple components: frontside trench, gate metal layer with openings, and backside trench. This segmentation allows each component to perform its specific function - the frontside trench provides initial isolation, the gate metal openings allow trench formation through self-aligned processing, and the backside trench completes the electrical isolation by removing conductive material between gates.
2Productivity
If transistor density is increased to improve computing power, then computing power increases, but gate electrode isolation becomes more difficult
Solution Approach 1:
The self-aligned processing methodology allows the isolation structure to define its own position automatically. The frontside trench and gate metal pattern serve as self-aligned masks that guide the formation of backside trenches, eliminating the need for separate photolithography alignment steps. This self-service capability enables precise isolation even as transistor density increases and feature sizes shrink.
3Reliability
If backside trenches are etched through gate metals, then gate electrode isolation is achieved, but manufacturing process complexity increases
Solution Approach 1:
The frontside trench is formed in advance before the gate metal layer is deposited. This preliminary action creates a pre-positioned isolation structure that serves as a mask and guide for subsequent self-aligned processing steps. The frontside trench is filled with dielectric material and planarized, preparing the surface for gate metal deposition while establishing the isolation geometry that will guide backside trench formation.
Solution Approach 2:
Instead of forming isolation structures from the front surface only, the patent inverts the approach by etching backside trenches from the back surface of the substrate through the gate metal layer. This inversion allows the isolation structure to be completed from both directions, with the backside trench removing conductive material between gates that cannot be isolated by frontside processing alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more efficient and cost-effective formation of transistors with improved performance, higher wafer yields, and reduced transistor heights, enabling increased computing power in integrated circuits.
Implementation Method 1
etching trenches in a substrate and through a gate metal
Data Source
AI summary
An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.


