Epitaxial Source/Drain Layout on Dielectric Substrates for Leakage Control

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Solution Overview

Problem

Existing multigate devices face challenges in optimizing reliability as they continue to scale down, with conventional methods not fully addressing issues related to gate control and short-channel effects, particularly in the integration of epitaxial source/drain structures.

Innovation Solution

The implementation of epitaxial source/drain structures with a dielectric substrate instead of a semiconductor substrate, which enhances performance by reducing leakage current and parasitic transistor formation, and involves a method of fabricating multigate devices using a flow chart process that includes epitaxial growth of semiconductor layers and formation of gate structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor substrates are used for multigate devices, then manufacturing compatibility is maintained, but leakage current increases and parasitic transistors form

Engineering Contradiction:
Improvedevice reliabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the source of leakage current and parasitic transistor formation by removing the semiconductor substrate and replacing it with a dielectric substrate. This eliminates the parasitic conduction paths that exist in conventional semiconductor substrates, directly addressing the harmful effects while maintaining device functionality through epitaxial source/drain structures.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a dielectric substrate as an intermediary between the epitaxial source/drain structures and the underlying support. This dielectric layer acts as a mediator that prevents direct electrical contact that would cause leakage, while still providing mechanical support and enabling the formation of high-performance multigate devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If device scaling is continued to improve integration density, then productivity increases, but gate control deteriorates and short-channel effects worsen

Engineering Contradiction:
Improveintegration densityVSAvoidgate control
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar gate control to three-dimensional multigate control by forming gates that wrap around the channel in multiple dimensions. This vertical and lateral gate wrapping provides enhanced electrostatic control over the channel, effectively suppressing short-channel effects even as devices continue to scale down in size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures including epitaxial semiconductor layers with different compositions (e.g., SiGe source/drain regions with silicon channels) to achieve both scaling and control. The engineered material composition gradients and heterostructures enable improved carrier mobility and gate control simultaneously.

Inventive Principle:
Principle #40Composite materials

3Reliability

If epitaxial source/drain structures are implemented to reduce leakage, then reliability improves, but manufacturing complexity increases

Engineering Contradiction:
Improveleakage reductionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the epitaxial source/drain structures with integrated strain features during the early fabrication stages, before gate formation. This preliminary strain engineering is built into the epitaxial growth process itself, allowing subsequent processing steps to proceed with standard techniques while the performance benefits are already established.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes in the epitaxial growth process, such as varying temperature, pressure, and composition gradients, to create optimized source/drain structures with built-in strain. By controlling these growth parameters, the patent achieves enhanced carrier mobility and reduced leakage without requiring additional complex post-processing steps.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the reliability and performance of multigate devices by reducing leakage current and enhancing strain characteristics, leading to better control over gate operations and reduced short-channel effects.

Implementation Method 1

epitaxial source/drain structures for multigate devices and methods of fabricating thereof

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11876135B2Epitaxial source/drain structures for multigate devices and methods of fabricating thereof
Publication Date: 2024.01.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11876135B2 patent drawing
  • US11876135B2 patent drawing
  • US11876135B2 patent drawing

AI summary

Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.