Conformal Protective Layer on Polysilicon for Silicide and Leakage Control
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Solution Overview
Problem
The thickness of protective layers in integrated circuits affects the performance of logic circuits, SRAM, and OTP memory, and residue materials from these layers can hinder the self-aligned silicide process, leading to issues with processing windows and leakage prevention.
Innovation Solution
A conformal protective layer is formed over polysilicon structures and spacers, with specific thickness variations to ensure adequate protection and facilitate subsequent removal processes, enhancing silicide formation and preventing leakage in OTP parts while allowing better processing windows for integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protective layer is formed in the OTP part to prevent leakage, then leakage prevention is improved, but the protective layer thickness affects the performance of logic circuit and SRAM
Solution Approach 1:
The patent applies different thicknesses of protective material to different regions: a first thickness in the OTP part for leakage prevention, and a second thickness in the logic/SRAM part for optimal performance. This local differentiation resolves the contradiction by allowing each region to have the specific protective layer characteristics it needs.
Solution Approach 2:
The protective layer is segmented into multiple regions with different thicknesses - a first region over the OTP part and a second region over the logic/SRAM part. This segmentation allows independent optimization of each region's protective layer thickness to meet different functional requirements.
2Reliability
If a protective layer is formed to protect polysilicon structure, then protection effectiveness is improved, but residue materials hinder the self-aligned silicide process
Solution Approach 1:
The patent controls the thickness parameter of the protective material within specific ranges (first thickness and second thickness) to balance protection effectiveness with removability. By optimizing these thickness parameters, the protective layer provides adequate protection while allowing complete removal without residues that would hinder subsequent silicide formation.
Solution Approach 2:
The protective layer is formed with sufficient thickness to provide adequate protection during processing, but not excessively thick to cause removal difficulties. The thickness is optimized to be just enough for protection while maintaining ease of complete removal.
3Reliability
If the protective layer thickness is increased to improve leakage prevention, then leakage prevention is improved, but the process window is reduced
Solution Approach 1:
Different thicknesses are applied to different regions: a greater first thickness in the OTP part for leakage prevention, and a controlled second thickness in the logic/SRAM part to maintain process window. This local quality differentiation resolves the contradiction between leakage prevention and process window.
Data Source
AI summary
A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.