Output Buffer Circuit With Gate-Voltage Clamping for High-Voltage MOSFET Drive
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Solution Overview
Problem
Existing output stage buffer circuits face challenges in reliably turning on power MOS transistors when the power supply voltage exceeds 20V due to increased substrate effects, leading to variations in output voltage and potential failure to meet specifications, especially when using N-channel MOS transistors.
Innovation Solution
The proposed output stage buffer circuit employs a configuration with a P-channel MOSFET, N-channel MOSFETs forming a push-pull circuit, a current mirror circuit, a constant-voltage circuit, and a bias circuit to clamp the gate voltage of the power MOS transistor, ensuring it remains below the power supply voltage, thereby reducing substrate effects and maintaining reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a power supply voltage higher than 20V is supplied to the drive circuit, then the output voltage can be increased to drive power MOS transistors with higher withstand voltage, but the substrate effect increases causing threshold voltage variations and unreliable operation
Solution Approach 1:
A clamp circuit is introduced as an intermediary between the power supply voltage source and the drive circuit. This clamp circuit includes a clamp transistor and a reference voltage source that work together to mediate the voltage relationship, ensuring the gate voltage remains within safe limits while allowing the power supply voltage to be higher than 20V. The clamp circuit acts as a buffer that prevents the harmful substrate effect from occurring.
Solution Approach 2:
The invention changes the voltage parameter at the gate of the power MOS transistor by introducing a clamp circuit that limits the gate voltage to a value lower than the power supply voltage. Specifically, the clamp circuit ensures that the gate voltage does not exceed a predetermined threshold (e.g., 20V), even when the power supply voltage is higher. This parameter change eliminates the substrate effect while maintaining the ability to use higher power supply voltages for improved power delivery.
2Ease of manufacture
If an inexpensive power MOS transistor with withstand voltage of 20V or less is used, then the cost is reduced, but the output voltage must be clamped below 20V limiting the power supply voltage
Solution Approach 1:
The clamp circuit serves as an intermediary that decouples the relationship between the power supply voltage and the gate voltage. It allows the power supply voltage to be higher than 20V (enabling use of inexpensive MOS transistors) while simultaneously ensuring that the gate voltage remains below the 20V threshold. This mediator component resolves the conflict between cost reduction and power capability.
Solution Approach 2:
The voltage control function is segmented into two independent parts: the power supply voltage (which can be higher than 20V) and the gate voltage (which is clamped to remain below 20V). The clamp circuit creates this segmentation by separating the power supply function from the gate drive function, allowing each to operate independently within their respective voltage ranges. This enables cost-effective design without sacrificing power capability.
3Reliability
If the gate voltage is clamped at a voltage lower than the power supply voltage, then the substrate effect is reduced improving reliability, but additional clamp circuit components are required increasing device complexity
Solution Approach 1:
The clamp circuit is designed as a minimal intermediary consisting of essential components (clamp transistor and reference voltage source) that perform the voltage limiting function with minimal added complexity. The reference voltage source can be implemented using standard integrated circuit elements, and the clamp transistor can be integrated into the existing drive circuit topology, thereby reducing the impact on overall device complexity while achieving the reliability improvement.
Data Source
AI summary
An output stage buffer circuit including a first P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), first to third N-channel MOSFETs, a constant-voltage circuit and a bias circuit. A source of the first P-channel MOSFET is connected to a power supply terminal. A source and a drain of the first N-channel MOSFET are respectively connected to a ground terminal and an output terminal. The first N-channel and P-channel MOSFETs constitute a push-pull circuit. The second N-channel MOSFET is disposed between a drain of the first P-channel MOSFET and a connection point between the drain of the first N-channel MOSFET and the output terminal. A source and a drain of the third N-channel MOSFET respectively receive from the constant-voltage circuit a constant voltage lower than a voltage received at the power supply terminal, and from the bias circuit a constant current. The second and third N-channel MOSFETs constitute a current mirror circuit.