Semiconductor Memory Assembly Layout for Orthogonal Pitch Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in aligning conductive lines, such as wordlines and digit lines, with CMOS circuitry in integrated memory arrays, particularly in achieving orthogonal alignment while managing different pitches and dimensions to optimize integration and reduce semiconductor real estate usage.
Innovation Solution
The implementation of FinFET arrangements with fins extending across CMOS regions on specific pitches, coupled with tailored gate lengths and spacings, allows for the alignment of conductive lines with circuit arrangements, ensuring matching dimensions and pitches to facilitate efficient integration of memory cells within the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar memory architectures are used, then manufacturing process is simpler, but integration density is limited and semiconductor space is wasted
Solution Approach 1:
The patent transitions from conventional planar (2D) memory architectures to three-dimensional FinFET structures, utilizing vertical fins extending from the substrate surface. This dimensional change enables orthogonal alignment of conductive lines with CMOS circuitry while significantly increasing integration density without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent modifies critical geometric parameters including fin pitch, gate length, and gate spacing to achieve precise orthogonal alignment. By carefully controlling these parameters, the conductive lines can be aligned at right angles to the fins while maintaining compatible pitch dimensions between the memory array and CMOS circuitry
2Area of stationary object
If conductive lines are aligned orthogonally with CMOS circuitry, then integration density is improved, but pitch matching between different structures becomes more difficult
Solution Approach 1:
The patent applies different pitch parameters to different regions of the device. The FinFET structure uses a first pitch optimized for vertical alignment, while the conductive lines use a second pitch optimized for horizontal alignment. This local differentiation of pitch parameters enables orthogonal alignment while maintaining manufacturability
Solution Approach 2:
By introducing the vertical dimension through FinFET fins, the patent decouples the pitch constraints that would otherwise exist in planar structures. The fin pitch can be independently optimized from the conductive line pitch, allowing orthogonal alignment without requiring identical pitch dimensions
Data Source
AI summary
Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.