Unified Gate Electrode Connection Line Vertical Channel Semiconductor
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Solution Overview
Problem
The fabrication of semiconductor devices with vertically oriented channels faces issues such as elevated connection line resistance, contact resistance, and gate-induced drain leakage, which impede reliable and cost-effective production.
Innovation Solution
A unified gate electrode/connection line and a buried bitline structure with an offset step region are introduced, allowing for self-aligned formation of lower source/drain regions and reducing contact resistance, while eliminating the need for separate fabrication processes and minimizing gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate fabrication processes are used for connection lines and gate electrodes, then connection lines can be formed, but connection line resistance increases due to natural oxides or contamination layers
Solution Approach 1:
The patent merges the connection line and gate electrode into a single unified structure formed by one continuous fabrication process. The gate electrode is formed as an extension of the connection line through simultaneous deposition and patterning, eliminating the separate formation steps and the harmful oxide/contamination interface between them.
2Productivity
If vertically oriented access elements are used, then integration density improves, but contact resistance between subsequently formed elements and access elements increases
Solution Approach 1:
The patent performs preliminary action by forming the connection line and gate electrode as a unified structure before forming the subsequently formed elements. This preliminary unified formation ensures that no oxide or contamination layers develop at the interface, and subsequent elements can be directly connected to this pre-formed unified structure with minimal contact resistance.
3Reliability
If conventional vertically oriented access elements are fabricated, then device functionality is achieved, but gate-induced drain leakage occurs
Solution Approach 1:
The patent converts the potentially harmful gate-induced drain leakage effect into a beneficial self-aligned formation mechanism. By using the gate electrode formation process to simultaneously define the connection line and create self-aligned structures, the patent eliminates the separate alignment steps that cause misalignment and subsequent leakage problems.
4Manufacturing precision
If multiple separate fabrication processes are used, then precise alignment can be achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements self-service through self-aligned formation where the gate electrode and connection line automatically align with each other and with subsequently formed elements through the unified fabrication process. The structures define their own alignment relationships during formation, eliminating the need for separate alignment steps and reducing manufacturing complexity.
Data Source
AI summary
An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.