Trench Power MOSFET Self-Aligned NDD Region Gate-Drain Capacitance

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Solution Overview

Problem

Conventional split-gate trench power MOSFETs face challenges in controlling the depth of the main gate, leading to large process windows, increased gate-to-drain capacitance, and performance degradation due to variations in trench depth and dielectric layer thickness.

Innovation Solution

The method involves forming a trench power MOSFET with a self-aligned N-type Doped Drain (NDD) region and a conductive field plate, where the NDD region is tilted to ensure overlap with the main gate, reducing the impact of process variations and minimizing gate-to-drain capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the depth of the trench and thickness of the dielectric layer are increased to ensure the epitaxy region is at the same level as the main gate, then the channel control is improved, but the gate-to-drain overlap increases and gate-to-drain capacitance increases

Engineering Contradiction:

Improveepitaxy region alignment with main gateVSAvoidgate-to-drain capacitance variation

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs preliminary doping to form the NDD region before trench formation. This preliminary action establishes a fixed reference structure that determines the eventual position of the epitaxy region, ensuring proper alignment with the main gate while controlling the overlap width. The NDD region serves as a pre-positioned marker that guides subsequent processing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The NDD region automatically serves multiple functions: it acts as a depth reference for trench etching, defines the epitaxy region position, and controls the gate-to-drain overlap. This self-aligning mechanism eliminates the need for separate alignment processes and reduces sensitivity to process variations in trench depth and dielectric layer thickness.

Inventive Principle:

Principle #25Self-service

2Ease of manufacture

If a large process window is used to ensure the epitaxy region is at the same level as the main gate, then manufacturing flexibility is improved, but the gate-to-drain capacitance and its variation increase

Engineering Contradiction:

Improveprocess windowVSAvoidgate-to-drain capacitance control

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent uses the NDD region as a feedback reference that automatically compensates for process variations. The trench depth is controlled relative to the NDD region position, creating a self-correcting mechanism that maintains consistent gate-to-drain overlap regardless of variations in trench depth or dielectric layer thickness.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the reference parameter from absolute trench depth to relative position with respect to the NDD region. This parameter transformation converts a process-sensitive dimension into a process-insensitive one, reducing the impact of manufacturing variations on gate-to-drain capacitance.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the main gate depth is increased to control the entire channel, then channel control is improved, but the depth control difficulty increases due to process variations

Engineering Contradiction:

Improvechannel controlVSAvoidmain gate depth control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent transitions from controlling main gate depth in one dimension (vertical trench depth) to controlling it relative to the NDD region position. By using the NDD region as a reference plane, the control mechanism moves from absolute depth specification to relative position specification, which is less sensitive to process variations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9178041B2Power MOSFET and methods for forming the same

Publication Date: 2015.11.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.