Nanosheet Bottom Isolation Structure for Punch-Through Prevention
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Solution Overview
Problem
The continued scaling of nanosheet FETs is limited due to erosion of the bottom isolation layer during conventional process flows, leading to punch-through and yield loss, and defective epitaxial growth from nanosheet sidewalls, resulting in device failures.
Innovation Solution
A composite bottom isolation structure with a bi-layer in the S/D region and a tri-layer inside the gate is formed, using sacrificial semiconductor materials, which prevents punch-through and improves epitaxial growth quality by replacing sacrificial layers with dielectric material and growing semiconductor buffer layers from a <100> surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional process flows are used for nanosheet FET fabrication, then manufacturing simplicity is maintained, but bottom isolation layer erosion occurs leading to punch-through and yield loss
Solution Approach 1:
The bottom isolation structure is divided into multiple layers including a first bottom isolation layer, a second bottom isolation layer, and a third bottom isolation layer with different materials and functions. This segmentation allows each layer to address specific erosion issues while maintaining overall structural integrity and preventing punch-through.
Solution Approach 2:
The patent employs composite material structure where the bottom isolation layers use different materials (e.g., silicon nitride, silicon oxide, silicon oxynitride) with complementary properties. This composite approach provides both mechanical support and chemical resistance against erosion during fabrication processes.
2Manufacturing precision
If epitaxial growth is performed from nanosheet sidewalls, then source/drain regions are formed, but defective epitaxial growth occurs resulting in device failures
Solution Approach 1:
A buffer layer is introduced as an intermediary between the nanosheet sidewalls and the source/drain epitaxial growth. This buffer layer mediates the growth process, providing a controlled interface that enables high-quality epitaxial growth while simplifying the overall manufacturing process by decoupling the complex sidewall growth challenges.
3Productivity
If device density is increased in nanosheet FETs, then performance is improved, but leakage current and parasitic capacitance management becomes more difficult
Solution Approach 1:
The patent extracts and addresses leakage current and parasitic capacitance issues by implementing specific isolation structures and gate designs that separate these problematic effects from the active device regions. This extraction allows high device density to be achieved while maintaining control over leakage and capacitance through dedicated structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents punch-through during fin recess and S/D epitaxy, enhances epitaxy process control and quality, and reduces device failures by maintaining the integrity of the bottom isolation layer and improving source/drain epitaxial growth.
Implementation Method 1
replacing the top sacrificial layer and the bottom sacrificial layer with dielectric material
Implementation Method 2
growing semiconductor buffer layers from a <100> surface
Data Source
AI summary
Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.