Analog Neural Memory Output Circuitry for Precise Synapse Weighting
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high computational parallelism and energy efficiency due to the lack of adequate hardware technology, particularly in implementing non-volatile memory arrays as synapses, which are bulky and inefficient.
Innovation Solution
Utilizing non-volatile memory arrays configured for individual programming, erasing, and reading without disturbing other memory cells, and enabling continuous analog programming, allowing precise tuning of synapse weights in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high computational parallelism, then computational capability is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital computational systems with analog neural memory circuits that perform multiply-accumulate operations natively. The analog circuit uses continuous voltage or current signals to represent data and weights, enabling parallel computation across multiple synapses simultaneously without the energy overhead of digital processing.
Solution Approach 2:
The neural memory array serves multiple functions: it stores weight values in non-volatile memory cells and simultaneously performs analog multiplication and accumulation operations. This multi-functionality eliminates the need for separate storage and processing units, reducing overall system energy consumption while maintaining high computational parallelism.
2Area of stationary object
If non-volatile memory arrays are used as synapses to reduce area, then device area is reduced, but programming precision deteriorates due to disturbance of other memory cells
Solution Approach 1:
The patent divides the memory array into independently addressable blocks or regions, allowing selective programming of specific synapses without affecting others. This segmentation enables precise weight tuning for individual connections while maintaining the compact non-volatile memory structure.
Solution Approach 2:
The patent implements preliminary verification and compensation steps before finalizing weight programming. The system performs read-verify-program cycles to ensure accurate weight values are written, and uses compensation techniques to correct for any cross-talk or disturbance effects, thereby achieving high programming precision in the compact memory array.
3Measurement precision
If separate multiplication and addition logic circuits are implemented, then computational accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges multiplication and addition operations into a single analog neural memory array. The memory cells naturally perform multiplication through their conductance characteristics, and the parallel summation of currents from multiple cells performs the addition operation simultaneously. This merging eliminates the need for separate logic circuits while maintaining computational accuracy through the physical properties of the analog system.
Data Source
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AI summary
Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In some embodiments, a common mode circuit is used with differential cells, W+ and W-, that together store a weight, W. The common mode circuit can utilize current sources, variable resistors, or transistors as part of the structure for introducing a common mode voltage bias.