Analog Neural Network Chip for High-Speed Processing
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Solution Overview
Problem
Existing artificial neural networks, whether digital or analog, face inefficiencies in processing speed and data sampling, leading to slower performance compared to networks with similar complexity and input data sampling.
Innovation Solution
A semiconductor chip is designed with an analogous electrical circuit implementing an artificial neural network based on a trained digital network, allowing simultaneous processing of input data across all nodes in a layer, thus outpacing digital networks with the same complexity and data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital artificial neural network is used, then the network can be trained and reconfigured, but the processing speed is slower compared to analog networks
Solution Approach 1:
The patent creates an analog copy of a trained digital neural network. The digital network is first trained to perform a specific task, then its architecture and weights are copied to create an analog implementation that operates faster while maintaining the same functionality. This resolves the contradiction by sacrificing reconfigurability (the copy is fixed) to gain processing speed.
Solution Approach 2:
The patent substitutes digital electronic circuits with analog electronic circuits for neural network processing. By replacing the digital switching and computing mechanism with analog continuous voltage/current processing, the system achieves faster operation at the expense of the ability to reprogram and retrain the network.
2Loss of time
If the first artificial neural network is less complex or uses subsampled input data, then it can provide output before the second network, but this limits processing capability
Solution Approach 1:
The patent replaces the digital first neural network with an analog implementation that has the same complexity as the second digital network. The analog circuit processes information continuously and simultaneously across all nodes, eliminating the sequential processing bottleneck of digital networks and enabling full-complexity networks to produce output at the same time without subsampling or simplification.
3Speed
If an analog neural network is implemented, then processing speed increases, but the network cannot be retrained or reconfigured
Solution Approach 1:
The patent performs the training action in advance using a digital neural network before the analog implementation is deployed. The digital network is trained offline, and once training is complete, the learned weights and architecture are transferred to the analog circuit which then operates at high speed without requiring further training. This separates the training phase (digital, flexible) from the execution phase (analog, fast).
Solution Approach 2:
The trained digital neural network is copied to create the analog implementation. The copy process transfers the learned knowledge (weights and architecture) from the digital domain to the analog domain, allowing the analog network to inherit the training results without needing to be retrained, thus achieving both speed and adaptability through the preliminary training of the source digital network.
4Adaptability or versatility
If digital networks process nodes sequentially, then reconfiguration is possible, but processing time increases
Solution Approach 1:
The patent substitutes the sequential digital processing mechanism with parallel analog processing. In the analog circuit, all nodes in a layer compute their outputs simultaneously using continuous electrical signals, eliminating the sequential node-by-node processing of digital networks. This achieves both high productivity through parallelism and maintains adaptability through the preliminary training of the digital counterpart.
Data Source
Figure 1a~1b
Figure 1c~3a
Figure 3b~5
AI summary
The invention relates to a method (120) for manufacturing a semiconductor chip, a semiconductor chip obtainable by the method (120), a device and a system comprising the semiconductor chip, and a method for manufacturing the system. The method (120) comprises at least the following steps: providing (121) a first trained digital artificial neural network (17); determining (122) a state of the first trained digital artificial neural network (17), the state comprising at least information about digital nodes of the first trained digital artificial neural network and information about a digital connection architecture between the digital nodes of the first trained digital artificial neural network (17); manufacturing (123) a semiconductor chip (40) comprising an analogous electrical circuit having an analogous artificial neural network (10) being designed according to the state of the first trained digital artificial neural network (17). The invention provides a fast processing artificial neural network (10) that may comprise the same complexity and that may use the same sampling of the input data as another artificial neural network, and that may complete operation during operation of the other artificial neural network.