Physical Realisation TRIZ Cases
- Convolution Transpose Hardware via Filter Segmentation and Interleaving
A convolution transpose implementation divides filters into sub-filters for parallel processing and interleaves output elements to form final tensors.
- Hearing Aid DNN Chip With Segmented CNN RNN Compute Units
A hearing aid processing chip uses separate compute units for convolutional and recurrent neural network layers to accelerate audio signal analysis.
- Neural Network Accelerator Candidate Selection Preprocessor
Preprocessor selects candidate rows from key matrix using maximum pointers to reduce computational load.
- Partial Tensor Correction for Neural Network Quantization
A partial tensor correction method applies per-input channel level adjustments to weight tensors during quantization.
- Analytic Loss Gradients for Hardware Neural Network Design
Symmetric solution submatrices determine analytic loss gradients in hardware neural networks.
- Neural Network Neuron Removal for Hardware Resource Reduction
Removing redundant neurons from trained models reduces hardware computational resources while maintaining classification accuracy.
- Memristor-Current Conveyor Artificial Neuron Unit
A memristor connects to a current conveyor input, which drives an artificial neuron to process signals.
- Memristive Learning Systems Stochastic Training
Transforming deterministic update equations into stochastic forms reduces design complexity and power overhead in memristive learning systems.
- Dilated Convolution Feature Map Splitting for Computational Complexity Reduction
Segmenting input feature maps allows independent local convolution processing, reducing memory access overhead while maintaining high resolution.
- Analog Neural Network Chip for High-Speed Processing
Analog neural network chip processes data in parallel to resolve the speed versus retraining trade-off.
- Nitrogen Sputtering for Memristor Metal Diffusion Control
Nitrogen plasma sputtering induces controlled metal diffusion into nitride layers to form memristive filaments.
- Gradient Descent Algorithm Near-Zero Learning Rate
A gradient descent algorithm uses a product value formulation to update model parameters accurately.
- CNN Building Blocks with Channel Split and Shuffle Units
Building blocks with channel split, convolution, concatenation, and shuffle units reduce computational complexity and energy consumption in neural networks.
- Neural Transformer Code Translation via Attention and Beam Search
A neural transformer model translates source code across programming languages using attention mechanisms.
- Partially Frozen Neural Network Weights for On-Device AI Efficiency
A partially frozen neural network divides weights into fixed and trainable cores to reduce hardware complexity.
- Deep Learning Pipeline Architecture for ANN Calculation Speed
Multi-stage pipeline architecture processes corrected input data and bias updates in parallel, reducing calculation time and memory capacity requirements.
- Neural Network Arithmetic Device with Dynamic Activation Function Circuit
An arithmetic device uses a look-up table to adjust logic level combinations for activation functions.
- Neural Network Internal Memory Caching for Data Transfer Bottlenecks
Caching feature maps in internal memory reduces data transfer time and improves operation processing speed.
- CNN Channel Pruning via Gradient Descent Masking
Gradient descent optimization guides a mask layer to prune convolutional neural network channels.