Hearing Aid DNN Chip With Segmented CNN RNN Compute Units
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Solution Overview
Problem
Deep neural network (DNN) processing on hearing devices is severely limited due to their restricted computational power and battery capacity, as existing hardware structures are not efficient enough to handle the compute and data-intensive requirements of both convolutional neural networks (CNN) and recurrent neural networks (RNN) layers.
Innovation Solution
A processing chip with a hardware architecture that includes separate compute units for CNN and RNN layers, a shared memory unit, and a data bus system with varying bandwidths to facilitate efficient data exchange, allowing for on-chip data storage and processing, thereby reducing the need for high clock frequencies and minimizing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processing units for neural networks run at very high clock rates to compensate for less efficient hardware structure, then processing speed is improved, but energy consumption increases beyond what hearing devices can sustain
Solution Approach 1:
The processing chip is segmented into specialized compute units: a first compute unit with hardware architecture adapted for processing convolutional neural network layers, and a second compute unit with hardware architecture adapted for processing recurrent neural network layers. This segmentation allows each unit to be optimized for its specific function, improving processing efficiency without requiring high clock rates across the entire system.
Solution Approach 2:
Different parts of the processing chip have different hardware architectures tailored to their specific processing needs. The first compute unit has architecture optimized for CNN operations while the second compute unit has architecture optimized for RNN operations. This local quality optimization enables efficient processing with lower energy consumption compared to a uniform high-performance architecture.
2Device complexity
If a single hardware structure is used for both CNN and RNN layers, then device complexity is reduced, but processing efficiency for both network types deteriorates
Solution Approach 1:
The processing chip is divided into distinct compute units: a first compute unit for CNN layers and a second compute unit for RNN layers. Each unit has hardware architecture specifically adapted to its processing requirements, maintaining manageable device complexity through functional separation while achieving high processing efficiency for both network types.
Solution Approach 2:
The processing chip provides universal support for both CNN and RNN architectures through its multi-functional design. The first compute unit handles CNN operations while the second compute unit handles RNN operations, enabling the single chip to efficiently process diverse neural network workloads without requiring separate dedicated hardware for each network type.
3Quantity of substance
If data is stored off-chip for neural network processing, then memory capacity is increased, but data access time and energy consumption increase
Solution Approach 1:
The processing chip merges compute units and memory units into a single integrated chip structure. The first and second compute units are both integrated on the same chip with access to on-chip memory resources, eliminating the need for frequent off-chip data access and reducing both data access time and associated energy consumption.
Solution Approach 2:
On-chip memory units serve as intermediaries between the compute units and external memory systems. These intermediate memory structures buffer data locally, allowing compute units to access frequently used data quickly without repeatedly accessing off-chip memory, thus reducing data access time and energy consumption.
Data Source
AI summary
A processing chip for processing audio signals using at least one deep neural network in a hearing device includes a first compute unit having a hardware architecture adapted for processing one or more convolutional neural network layers of the at least one deep neural network, a second compute unit having a hardware architecture adapted for processing one or more recurrent neural network layers of the at least one deep neural network, a shared memory unit for storing data to be processed in respective layers of the at least one deep neural network, the shared memory unit comprising a memory controller configured for running on a memory controller clock frequency that is higher than a compute unit clock frequency of both the first compute unit and the second compute unit, and a data bus system for providing access to the shared memory unit.