AND Flash Memory Level Shifter Circuit for Bit Line Voltage
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Solution Overview
Problem
Conventional AND type flash memory experiences inefficiencies in programming and erasing operations due to the page buffer's inability to provide high enough driving voltages, limiting the efficiency of memory cell operations.
Innovation Solution
Incorporating level shifter circuits between page buffers and bit lines to generate driving signals by shifting voltage values, ensuring inhibited bit lines receive sufficient voltage during programming and erased bit lines receive adequate voltage during erasing, thereby enhancing operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the page buffer provides control signals with digital logic voltage levels, then the circuit design is simple, but the driving voltage is insufficient for effective programming and erasing operations
Solution Approach 1:
A level shifter circuit is introduced as an intermediary component between the page buffer and the bit line. The level shifter receives control signals from the page buffer and converts them to higher voltage driving signals, thereby resolving the voltage insufficiency without requiring the page buffer itself to generate high voltages. This mediator approach maintains the simplicity of the page buffer while achieving the required driving power.
Solution Approach 2:
The level shifter circuit changes the voltage parameter of the control signals by shifting them from digital logic levels to higher driving voltage levels. This parameter transformation enables the bit line to receive sufficient voltage for effective programming and erasing operations while keeping the original control signal generation simple.
2Productivity
If the page buffer provides high voltage driving signals directly, then the programming and erasing efficiency is improved, but the page buffer design becomes more complex
Solution Approach 1:
The level shifter circuit serves as a dedicated intermediary that handles the voltage conversion task, allowing the page buffer to focus on control signal generation. This division of labor improves programming and erasing efficiency through adequate voltage delivery while preventing the page buffer from becoming overly complex.
3Productivity
If the bit line receives insufficient voltage during programming and erasing, then the circuit design is simpler, but the operational efficiency of memory cells deteriorates
Solution Approach 1:
The level shifter circuit acts as a voltage amplification intermediary that receives low-voltage control signals from the page buffer and generates high-voltage driving signals for the bit line. This ensures adequate voltage is delivered to improve memory cell programming and erasing efficiency without requiring the entire system to be designed for high voltage from the start.
Data Source
AI summary
An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.