Angled Conductive Layers in Semiconductor Storage Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high integration and efficient manufacturing processes, particularly in forming stacked conductive layers and contacts without short circuits and increasing the number of manufacturing steps.
Innovation Solution
The semiconductor storage device employs a configuration with stacked memory cell arrays and conductive layers, where the conductive layers in the hookup regions are angled and insulated, and via holes are formed selectively to align the end portions of sacrificial layers, allowing for high integration while preventing short circuits and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked conductive layers and contacts are formed in conventional semiconductor storage devices, then integration density is improved, but the number of manufacturing steps increases and short circuits may occur
Solution Approach 1:
The patent forms angled conductive layers and insulating layers in a predetermined sequence before final contact formation. The insulating layers are prepared in advance with specific angles to guide subsequent conductive layer deposition, preventing short circuits before they can occur during final assembly.
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between stacked conductive layers and contacts. These insulating layers act as mediators that prevent direct contact between conductive elements, eliminating short circuit risks while maintaining the stacked configuration for high integration.
2Reliability
If stacked conductive layers are formed with precise alignment, then short circuits are prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs angled conductive layers and insulating layers with specific inclination angles rather than vertical stacking. This angular configuration provides natural alignment guidance and tolerance, reducing the precision requirements while ensuring proper positioning and preventing short circuits between stacked elements.
3Quantity of substance
If the number of stacked memory cell arrays is increased, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the stacked structure into modular units with repeating patterns of conductive layers and insulating layers at specific angles. This segmentation allows standardized manufacturing processes to be applied repeatedly, reducing overall manufacturing complexity even as the number of stacked arrays increases.
Data Source
AI summary
A semiconductor storage device includes a substrate with a memory cell region and a first region to one side of the memory cell region. A first memory cell layer is on the substrate. A second memory cell layer is between the first memory cell layer and the substrate. A plurality of first conductive layers are stacked on each other in the first memory cell layer. A plurality of second conductive layers are stacked on each other in the second memory cell layer. A plurality of first contacts are above the first region of the substrate, extending through second conductive layer from the substrate to the first memory cell layer. The contacts are electrically insulated from the second conductive layers and electrically connected to ends of the first conductive layers in the first region.