Angled Etching for Asymmetric Transistor Source/Drain Formation
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Solution Overview
Problem
The microelectronic industry faces challenges in achieving higher performance, lower costs, and increased miniaturization of integrated circuit components due to inefficiencies in the fabrication processes, particularly in forming microelectronic transistor source and drain regions.
Innovation Solution
The use of angled etching techniques to reduce masking steps and form asymmetric spacers on microelectronic transistors, allowing for the creation of asymmetric source/drain configurations and raised doped regions through regrowth processes, which enhance transistor performance by controlling external resistance and overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional masking steps are used to form source and drain regions, then manufacturing precision is maintained, but device complexity and production time increase
Solution Approach 1:
The fabrication process is segmented into distinct phases: forming asymmetric spacers through angled etching, followed by selective doping in exposed regions. This segmentation allows the source and drain regions to be formed in separate controlled steps, reducing the need for multiple masking operations while maintaining precision through the geometric constraints of the angled etch pattern.
Solution Approach 2:
Asymmetric spacers are formed in advance through angled etching before the doping process. This preliminary action establishes the precise boundaries for source and drain region formation, eliminating the need for subsequent masking steps to define these regions. The spacers serve as pre-positioned masks that guide the doping process.
2Reliability
If symmetric source/drain configurations are used, then manufacturing simplicity is maintained, but transistor performance is limited
Solution Approach 1:
The patent deliberately introduces asymmetry in the source and drain configurations by forming asymmetric spacers through angled etching. This asymmetry allows different doping concentrations, depths, or extensions in the source and drain regions, enabling optimized transistor performance characteristics such as improved drive current, reduced short-channel effects, or enhanced switching characteristics that cannot be achieved with symmetric configurations.
Solution Approach 2:
Different local properties are applied to the source and drain regions through the asymmetric spacer configuration. One side may have higher doping concentration, different doping depth, or varying extension under the gate, allowing each region to be optimized for its specific functional requirements while maintaining overall device performance.
3Adaptability or versatility
If angled etching is used to form asymmetric spacers, then design flexibility increases, but manufacturing precision requirements increase
Solution Approach 1:
The angled etch process parameters (angle, depth, termination criteria) can be adjusted to achieve different spacer geometries and corresponding source/drain configurations. By changing these parameters, the same basic process flow can accommodate various design requirements, providing flexibility while managing precision requirements through controlled parameter variation rather than process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of masking steps, improves transistor performance by achieving lower overlap capacitance and matched external resistance, and increases design flexibility, thereby addressing the industry's goals of higher performance and miniaturization.
Implementation Method 1
performing an angled etch directed toward the transistor gate first sidewall to form a first transistor gate spacer abutting the first sidewall of the transistor gate
Implementation Method 2
form raised doped regions by regrowth
Data Source
AI summary
The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.