Angled-Gate Transistor Layout for Density and Short-Channel Control
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Solution Overview
Problem
As the semiconductor industry continues to scale features in integrated circuits (ICs), optimizing transistor performance and reducing short-channel effects like leakage and subthreshold swing becomes increasingly challenging, particularly due to the limitations of conventional planar transistor architectures.
Innovation Solution
The implementation of transistors with angled gates, which increase effective gate length while allowing for reduced gate widths, thereby enhancing density and minimizing short-channel effects, is proposed. This design is applicable to both FinFETs and nanoribbon transistors and can be optimized for low-temperature operation to further decrease transistor footprints without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistor architectures are used, then manufacturing simplicity is maintained, but short-channel effects like leakage and subthreshold swing increase
Solution Approach 1:
The patent transitions from conventional planar (2D) gate structures to three-dimensional FinFET and nanoribbon architectures. The FinFET uses a vertical fin structure where the gate wraps around three sides of the channel, while the nanoribbon uses a fully surrounding gate structure. This dimensional change increases the effective gate control area without increasing the footprint, thereby reducing short-channel effects while maintaining manufacturing feasibility through established semiconductor processes.
Solution Approach 2:
The gate structure is nested around the channel region in both FinFET and nanoribbon configurations. In FinFET, the gate wraps around the vertical fin; in nanoribbon, the gate completely surrounds the channel. This nesting arrangement maximizes gate control over the channel while minimizing the device footprint, effectively suppressing short-channel effects without requiring larger manufacturing areas.
2Quantity of substance
If transistor size is reduced to increase density, then capacity increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
By moving to 3D FinFET and nanoribbon structures, the patent achieves higher transistor density within the same footprint. The vertical fin and surrounding gate configurations allow more transistors to be packed into limited chip area while maintaining effective gate control, thus preserving performance even as density increases.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials and metal gate electrodes in the gate stack, combined with carefully engineered semiconductor channel materials. These composite structures enable better electrical control and performance optimization at scaled dimensions, allowing continued performance improvement as transistor density increases.
3Area of moving object
If gate width is reduced to increase density, then transistor footprint decreases, but short-channel effects worsen
Solution Approach 1:
The patent compensates for reduced gate width by utilizing vertical dimension in FinFET structures and three-dimensional surrounding gates in nanoribbon structures. This allows the effective gate control length to be maintained or increased even as the planar footprint is reduced, thereby suppressing short-channel effects while achieving higher density.
Solution Approach 2:
The FinFET structure introduces asymmetry with its vertical fin configuration, and the nanoribbon uses a fully symmetric surrounding gate. Both asymmetric and symmetric 3D configurations provide enhanced gate control compared to conventional planar structures, allowing reduced footprint without sacrificing control over short-channel effects.
Data Source
AI summary
IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein. A transistor is referred to as having an “angled gate” if an angle between a projection of the gate of the transistor onto a plane of a support structure (e.g., a die) over which the transistor is implemented and an analogous projection of a longitudinal axis of an elongated structure (e.g., a fin or a nanoribbon having one or more semiconductor materials) based on which the transistor is built is between 10 degrees and 80 degrees. Transistors having angled gates provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.