Angled Transistor Layouts for Higher IC Density and Routing
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is optimizing transistor performance and contact efficiency as feature scaling continues, particularly in non-planar architectures like FinFETs and nanoribbon transistors, where conventional orientations limit density and efficiency.
Innovation Solution
Implementing angled transistors and angled routing tracks in IC devices, where the direction of carrier transport is neither perpendicular nor parallel to the support structure edges, allowing for increased cross-section for carrier transport and reduced footprint while maintaining drive current, and optimizing for low-temperature operation to further decrease transistor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional transistor orientations are used in non-planar architectures, then manufacturing is simplified, but transistor density and contact efficiency are limited
Solution Approach 1:
The patent applies asymmetry by orienting transistors at non-conventional angles (e.g., 45 degrees) relative to the substrate edges, breaking the traditional symmetric alignment. This asymmetric orientation increases the effective cross-section for carrier transport and improves contact efficiency while maintaining manufacturing feasibility through adapted fabrication processes
2Quantity of substance
If transistor size is reduced to increase density, then capacity increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
The patent transitions from conventional planar scaling to a multi-dimensional approach by angling transistors in three-dimensional space. This dimensional change allows the effective channel width to increase diagonally across the substrate, providing additional scaling dimension that improves performance without reducing the physical footprint, thus maintaining density while optimizing individual device performance
3Reliability
If angled transistors are implemented, then effective cross-section for carrier transport increases, but routing alignment becomes more challenging
Solution Approach 1:
The patent merges the transistor orientation and routing track alignment by implementing routing tracks at matching angles (e.g., 45 degrees). This consolidation of angular parameters simplifies the manufacturing process by reducing the number of distinct alignment references needed, while simultaneously maximizing carrier transport efficiency through optimized contact geometry
4Quantity of substance
If feature scaling continues, then capacity increases, but adverse effects of scaling become more significant
Solution Approach 1:
The patent changes the geometric parameters of transistors by introducing angular orientation as a new degree of freedom. This parameter change allows optimization of the effective channel dimensions independent of the lithographic feature size, enabling continued capacity increases while mitigating scaling adverse effects such as reduced carrier mobility and increased leakage through improved geometric efficiency
Data Source
AI summary
IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.