Angled Transistor Layout for Higher-Density Memory Cells
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Solution Overview
Problem
Conventional memory devices face limitations in transistor density due to the alignment constraints of transistors with control lines, leading to compromised performance and increased complexity and cost in scaling, as well as lattice mismatch issues when attempting to increase memory cell density.
Innovation Solution
The use of angled transistors formed through a pair of unaligned wafers, where the semiconductor structure's crystal direction is not parallel or perpendicular to the substrate's crystal direction, allowing for higher transistor density without compromising performance by avoiding lattice mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors are aligned with control lines in conventional memory devices, then manufacturing process is simpler, but transistor density is limited and performance is compromised
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the crystal directions of the first and second wafers by a non-standard angle (e.g., 27 degrees instead of parallel or perpendicular). This asymmetric orientation allows transistor channels to be angled relative to control lines, increasing the number of transistors that can be packed into the memory device while maintaining proper electrical functionality through careful design of word lines and bit lines at corresponding angles.
Solution Approach 2:
The patent introduces angular orientation as an additional dimension for transistor arrangement. Instead of limiting transistors to conventional horizontal/vertical alignments with control lines, the invention utilizes angled orientations (e.g., 27 degrees) to create new spatial configurations. This dimensional change allows transistors to be arranged more efficiently in the available space, increasing density without compromising manufacturing precision through standard alignment procedures.
2Productivity
If transistor density is increased in conventional memory devices, then storage capacity improves, but lattice mismatch issues arise and performance is compromised
Solution Approach 1:
The patent changes the crystal orientation parameter between wafers from conventional parallel or perpendicular alignments to a specific angled relationship (e.g., 27 degrees). This parameter change allows the transistor channels to be oriented at angles that optimize space utilization while maintaining crystallographic compatibility. The specific angular relationship preserves lattice matching, preventing defects that would otherwise arise from high-density packing, thereby maintaining device reliability and performance.
3Ease of manufacture
If conventional wafer alignment is used, then manufacturing process is straightforward, but space utilization is inefficient and transistor density is limited
Solution Approach 1:
The patent implements asymmetry by deliberately using non-standard angular relationships (e.g., 27 degrees) between wafer crystal directions instead of conventional parallel or perpendicular alignments. This asymmetric approach maximizes space utilization by allowing transistor channels to be oriented at optimal angles relative to control lines, enabling more transistors to fit within the same wafer area while maintaining manufacturability through controlled deposition and lithography processes.
Solution Approach 2:
The patent utilizes angular orientation as an additional spatial dimension to improve area utilization. By orienting transistor channels at angled relationships (e.g., 27 degrees) rather than strict horizontal/vertical alignments, the invention effectively packs transistors more efficiently into the available wafer area. This dimensional approach to space utilization increases transistor density without complicating the manufacturing process, as the angled orientations are achieved through standard fabrication techniques applied to pre-aligned wafers.
Data Source
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AI summary
IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.