ANN Neuron Computation Acceleration via Bit Segmentation
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Solution Overview
Problem
Existing technologies face challenges in efficiently processing artificial neural networks (ANNs) due to high computational loads, power consumption issues, and limitations in programming Field Programmable Gate Arrays (FPGAs) for large-scale ANN computations.
Innovation Solution
A system and method that accelerate neuron computations in ANNs by splitting input values and weights into parts with fewer bits, selectively performing mathematical operations, and skipping redundant bitwise operations to reduce computational load and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GPUs are used to process large ANNs due to higher throughput capacity, then computational speed is improved, but power consumption increases excessively
Solution Approach 1:
The patent segments the bit representation of input values and weights into multiple parts (e.g., splitting an 8-bit value into four 2-bit parts). This segmentation allows the system to perform computations on smaller bit segments, reducing the overall computational complexity and power consumption while maintaining acceptable accuracy through selective processing of significant parts.
Solution Approach 2:
The patent applies partial action by selectively performing mathematical operations only on significant parts of the bit representations. Not all bit parts are processed equally - the system identifies and processes only the most significant parts that contribute meaningfully to the computation result, skipping redundant operations on less significant parts to reduce power consumption.
2Productivity
If FPGAs are programmed to perform parallel computations for ANNs, then computational efficiency is improved, but programming complexity increases significantly
Solution Approach 1:
The patent creates a universal processing framework that can handle different ANN operations (multiplications, accumulations, threshold comparisons) using a common bit-partitioning approach. This universal method works across various FPGA configurations and ANN architectures, reducing the need for custom programming for each specific case and thereby lowering programming complexity.
Solution Approach 2:
The patent changes the parameter representation from full-bit values to segmented bit parts with different significance levels. By transforming the computational parameters into this segmented form, the system enables simpler hardware logic and more straightforward programming patterns that are easier to implement and maintain on FPGAs.
3Measurement precision
If full precision bitwise operations are performed on all input values, then computational accuracy is maintained, but computational load increases
Solution Approach 1:
The patent applies local quality by treating different bit parts of the input values differently based on their significance. The most significant parts are processed with full precision to maintain accuracy, while less significant parts are processed with reduced precision or skipped entirely. This localized differentiation maintains overall computational accuracy while significantly reducing the total computational load.
Data Source
AI summary
Systems and methods for accelerating neuron computations in artificial neural network (ANN) are provided. An example method may comprise receiving, for calculation of a neuron of an ANN, a plurality of first values represented by A bits and a plurality of second values represented by B bits, splitting each value of the plurality of the first values into a set of parts, a count of bits of each of set of parts being less than A, to obtain a set of pluralities of parts, selectively performing mathematical operations on a first plurality of the set of pluralities and the plurality of the second values to obtain a first result, selectively performing further mathematical operations on further pluralities of the set of pluralities and the plurality of the second values to obtain further results, and determining, based on the first result and the further results, an output of the neuron.