Anti-Diffusion Through-Hole Substrate Using EPIG or ENEPIG Plating
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Solution Overview
Problem
Conventional substrate manufacturing processes face inefficiencies and poor coverage of anti-diffusion layers due to multiple deposition steps, leading to gaps and diffusion of metals, which affect signal transmission quality and increase resistance.
Innovation Solution
Utilizing an Electroless Palladium Immersion Gold (EPIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer as the anti-diffusion layer, which is completely attached to a first metal layer, preventing diffusion and allowing for high-purity second metal layers without gaps, even in high aspect ratio through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PVD deposition steps are used to form the anti-diffusion layer, then the anti-diffusion function is provided, but the manufacturing process becomes time-consuming and complicated
Solution Approach 1:
The patent extracts the anti-diffusion function from the complex multi-layer PVD structure and implements it through a simpler electroless plating process. The copper layer itself is utilized to provide the anti-diffusion function when in contact with the gold layer, eliminating the need for separate electroless nickel and electroless palladium layers, thus simplifying the manufacturing process while maintaining the anti-diffusion reliability.
Solution Approach 2:
The patent changes the deposition method from physical vapor deposition (PVD) to electroless plating. This parameter change in the deposition process enables the anti-diffusion layer to be formed in a single step rather than multiple steps, significantly improving manufacturing efficiency while maintaining the required anti-diffusion function.
2Manufacturing precision
If PVD process is used to deposit anti-diffusion layer in through holes with high aspect ratios, then the layer is formed, but the coverage is poor and gaps appear
Solution Approach 1:
The patent replaces the physical vapor deposition (mechanical/physical process) with electroless plating (chemical process). The electroless plating process uses chemical reduction to deposit metal layers uniformly throughout the through holes, including high aspect ratio holes, ensuring complete coverage without gaps that are characteristic of PVD processes.
Solution Approach 2:
The patent changes the deposition mechanism from physical vapor deposition to electroless plating. This parameter change enables the anti-diffusion layer to be deposited uniformly throughout the entire surface and within high aspect ratio through holes, achieving complete coverage and eliminating the gap formation issue inherent in PVD processes.
3Reliability
If copper metal layer is used as the first metal layer, then the electrical connection is provided, but the copper may diffuse to the gold layer reducing purity
Solution Approach 1:
The patent converts the potentially harmful copper diffusion into a beneficial configuration by carefully controlling the layer structure and interfaces. The copper layer is positioned to provide excellent electrical connection, and through the electroless plating process and proper interface design, the harmful diffusion effect is minimized while maintaining the electrical benefits of copper.
Solution Approach 2:
The patent introduces an intermediary approach where the electroless plating process creates a controlled transition between the copper layer and the gold layer. This intermediary process ensures that any potential diffusion is controlled and managed, preventing direct harmful interaction between copper and gold while maintaining electrical connectivity.
4Reliability
If multi-layer anti-diffusion structure is formed, then the anti-diffusion function is enhanced, but the manufacturing time and cost increase
Solution Approach 1:
The patent extracts the essential anti-diffusion function from the complex multi-layer structure and implements it through a simplified single-step electroless plating process. By removing the unnecessary electroless nickel and electroless palladium layers, the patent maintains the required anti-diffusion performance while significantly reducing manufacturing cycle time and cost.
Solution Approach 2:
Instead of adding multiple layers to achieve anti-diffusion function, the patent inverts the approach by using a single electroless plating step that achieves the same or better anti-diffusion performance with fewer layers, thereby reducing manufacturing time and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures reliable electrical connections with reduced impedance and improved signal quality by maintaining high purity of the second metal layer, simplifying the manufacturing process and reducing costs.
Implementation Method 1
an anti-diffusion layer plated on the first metal layer is formed within each of the through holes, and the anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer
Implementation Method 2
an anti-diffusion layer 40′ is plated on the glass substrate 10′ by physical vapor deposition (PVD)
Implementation Method 3
some of the circuits on the substrate may be affected by the diffusion effect of other metals
Data Source
AI summary
An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.