Anti-Phase Sampling Capacitor Input for Low-Noise ADCs
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Solution Overview
Problem
Existing analog to digital converter (ADC) systems face challenges in reducing power dissipation and noise due to the kick-back transient current when sampling switches are closed, particularly in pipelined ADCs using switched capacitor techniques, which affects the accuracy and efficiency of the sample and hold process.
Innovation Solution
The implementation of two sampling capacitors operating in anti-phase, where the reset phase and sampling phase of one channel occur during the hold phase of the other channel, allowing for a longer hold phase and reduced power dissipation without shortening the sampling phase, thereby minimizing the requirements on the external amplifier and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the sampling capacitor is reset to a fixed value before each sampling period, then the kick-back transient current is reduced, but the hold phase duration is shortened
Solution Approach 1:
The patent divides the single sampling capacitor into two separate capacitors (first sampling capacitor and second sampling capacitor) that operate in alternating phases. While one capacitor is in the hold phase, the other undergoes reset and sampling. This segmentation allows the reset operation to occur without reducing the hold phase duration of the active capacitor, thereby resolving the contradiction between reducing kick-back current and maintaining hold phase length.
2Object-generated harmful factors
If a buffer amplifier is added before the sampling switch, then the transient current kick-back is attenuated, but the total noise and power dissipation increase
Solution Approach 1:
Instead of adding a buffer amplifier, the patent segments the sampling function into two capacitors operating in parallel with alternating phases. This approach attenuates the kick-back transient current by distributing the sampling load across two capacitors without introducing additional active components, thereby reducing power dissipation while still mitigating the harmful transient effects.
3Measurement precision
If the hold phase is extended to improve processing accuracy, then the sampling phase duration must be reduced, but this increases the requirements on the external amplifier
Solution Approach 1:
The patent segments the sampling and hold functions across two capacitors operating in parallel. Each capacitor alternates between sampling phase and hold phase, allowing both phases to maintain adequate duration without compromising the other. This eliminates the need to extend the hold phase at the expense of sampling time, thereby maintaining sampling accuracy without increasing amplifier requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach doubles the available time for the hold phase, reducing power dissipation in the internal circuitry and minimizing the requirements on the external amplifier, while maintaining the duration of the sampling phases, thus enhancing the accuracy and efficiency of the ADC system.
Implementation Method 1
The sampling block usually consists of a capacitor 100 that is connected to the input signal during part of clock period and disconnected from the input signal during the rest of the period. The clock signal controls the switch 101. During the high phase, S, of the clock signal, the switch is closed and the input is connected to the sampling capacitor 100. At the high to low transition of the clock signal, the switch is opened and the value of the input signal at that point in time is stored on the capacitor
Data Source
AI summary
A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.