Computing Operations For Integral Formation TRIZ Cases

Charge reservoirs and charge movement devices perform multiplication without digitization, cutting conversion noise, latency, and energy use.

Injected signal correlation tunes sigma-delta resonator frequencies despite process and temperature drift, improving notch alignment and noise performance.

Multiple DACs split and recombine frequency portions through IQ mixing to expand bandwidth while preserving signal quality.

Multiple DACs split and frequency-interleave sampled signals to expand analog bandwidth while pre-equalization limits cross-talk distortion.

A half-frequency input clocking scheme cuts switching power and charge loss in a switched-capacitor integrator while improving impedance and linearity.

A feedback-gain-dependent compensation capacitor improves op-amp phase margin and bandwidth for stable high-speed CMOS image sensor circuits.

Charge-redistribution capacitor circuits compute Fourier-type functions directly in analog form, avoiding ADC/DAC speed, power, and area penalties.

A mode device reconfigures integrators and feedback paths so one sigma-delta ADC supports low-IF and NZIF receivers without duplicate hardware.

A coarse-fine threshold ramp cuts detector-delay overshoot and keeps switched-capacitor ADC ramps linear across voltage variation.

Cancelling capacitors offset MOSFET switch parasitics in tunable active RC resonators, preserving high Q across wide frequency ranges.

Clocked multiplexers and paired latches cut DFE correction delay while improving ISI cancellation and clock recovery in serial links.

A matched transconductance loop adjusts output resistance to keep integrator phase stable across process, voltage, and temperature shifts.

A comparator and capacitor integrator capture time of flight and reflected flux in one pulse, cutting power use and reconstruction delay.

Adjustable varactors and blocking capacitors linearize voltage-dependent input capacitance to cut harmonic distortion in precision RF and analog fronts.

An integrator with differential floating sampling suppresses common-mode disturbance and charge injection to stabilize switched-capacitor outputs.

An adjustable integrator and variable gain stage tune cut-off frequency while preserving the linearity of resistive low-pass filtering.

A switching and anti-saturation circuit keeps HDD input buffer thresholds stable across 1.8V to 5V while preserving switching speed.

A four-phase switched-capacitor cycle masks residual charge and separates auxiliary and main references to cut modulation noise and gain error.

A matched amplifier feedback loop adjusts output resistance to keep integrator phase stable across PVT variation and wide tuning ranges.

Adjustable switch and varactor bias levels cancel input capacitance variation, cutting harmonic distortion in high-dynamic-range RF and analog front-ends.

Adjustable bias-controlled varactors cancel input-dependent capacitance, cutting harmonic distortion in high-dynamic-range RF and analog front ends.

A comparator and reference-current capacitor scheme detects touch capacitance changes without integrator offset, improving sensing reliability.

Filtering and integration stages raise capacitive sensing SNR, helping touch and proximity circuits separate weak signals from noise.

Adjustable varactors and bias circuits counter linear and parabolic capacitance nonlinearity, reducing distortion in high-dynamic-range RF fronts.

Lock-out-controlled integration converts event timing into voltage while ensuring minimum integration time for low-noise, low-power radiation readout.

Charge-redistribution capacitor circuits compute functions such as DFT directly in analog form, cutting converter-related delay, power, and area.

By converting charge-transfer sensing into frequency output, this case avoids exponential voltage rise and enables precise linear capacitance measurement.

Shorting differential amplifier outputs at the start of comparison reduces settling errors while preserving low-offset switched capacitor operation.

A varactor with DAC-based analog control replaces series switching resistance, enabling high-Q digital capacitance tuning for filters and antenna matching.

A level-shifting capacitor lets the pre-amplifier run at lower supply voltage while preserving input common-mode range and reducing thermal noise.

Stacked thin-oxide transistor switches with level-shifted biasing reduce voltage stress and parasitic capacitance in VCO tuning circuits.

Weighted PWM drives paired switchable capacitors to improve tuning resolution while reducing spurious signals and phase noise.

A compensation capacitor adds zero compensation to higher-order integrators, reducing Class-D amplifier distortion while preserving phase margin.

NDL filtering suppresses impulsive noise while staying linear in normal conditions, improving signal-to-noise ratio with lower power and complexity.

Alternating constant-voltage charging and reference discharging calibrate RC values accurately even when the sampling clock duty ratio is unbalanced.

Offset sampling capacitors and zero-crossing detection cut amplifier offset and power while preserving low-noise, high-dynamic-range sampling.

Dual cancellation paths cut integrator output swing in sigma-delta ADC loop filters while preserving signal transfer and noise behavior.

Delayed and inverted control signals improve switched-capacitor timing, avoiding junction capacitance and accidental turn-on in VCO tuning.

Two integrators keep analog signal amplitude within the ADC range, avoiding truncation and noise loss during high-speed data detection.

Switched capacitor interpolation is split across capacitor branches and dynamic switches to shrink receiver circuits while preserving data accuracy.

Parallel saturation-mode FETs redirect second-harmonic currents in a differential sampling circuit, improving ADC SFDR at high input frequencies.

A level-crossing detector and linear ramp output reduce delay and noise errors, improving sampled-data voltage accuracy and power efficiency.

Charge transfer between diodes, transistors, and capacitors enables signal integration without op-amps, reducing power use and added noise.

Dummy capacitive elements track switch parasitics in a differential CDS integrator to cut leakage and improve ADC linearity and resolution.

A constant voltage module holds PMOS gate-source voltage steady, enabling low-voltage analog sampling with high linearity and low distortion.

A self-biased comparator stage merges bias and comparison functions to cut power and area while keeping oscillator frequency stable across corners.

Switchable compensation capacitance boosts reset-mode slew rate and bandwidth in capacitive sensing while reducing circuit size.

Feedback from the switch output limits high-side NMOS slew rate, curbs inrush current, and lets multiple switches share one charge pump.

Alternating two sampling capacitors lets one ADC channel hold while the other resets and samples, cutting kick-back noise and power dissipation.

Double-sampled switched-capacitor resistors let a Type-III DC-DC compensation filter track switching frequency, extend bandwidth, and cut trim needs.

A single op-amp switched capacitor circuit combines integration and summing to cut power, size, and cost while maintaining high-speed signal processing.

A two-stage differential S/H circuit integrates positive and negative pulses concurrently to reduce noise saturation, pulse overlap, and test time.

Impedance transformers and SiGe BiCMOS bipolar transistors reduce RF signal distortion and insertion loss without costly compound-semiconductor processing.

Flexible integration intervals let radiation sensors blank stray light, average multiple returns, and extend sensitivity and range without added size or power.

Voltage equalization at the switching node suppresses leakage-current error, keeping switched capacitance accurate and stable.

Voltage amplification and reset recycle charge to emulate large on-chip capacitance with less area, leakage impact, and a wider input range.

Phase-opposed correlated double sampling removes offset and flicker noise while keeping phase shift stable in switched-capacitor stages.

A parallel coarse and main switch with staggered clock durations cuts charge injection and clock feed-through without matching overhead.