Switched-Capacitor Integrator Clocking for Lower Charge Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Double sampling networks in switched-capacitor integrators are not power efficient due to higher charge loss caused by switching every clock cycle, which affects noise performance and power consumption.
Innovation Solution
Implementing a different clocking scheme where two different sets of input sampling switches are switched every two clock cycles, reducing switching power and improving distortion performance by half the switching frequency, thereby increasing power efficiency and equivalent input impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If switching every clock cycle is used in double sampling networks, then sampling accuracy is improved, but power consumption increases due to higher charge loss
Solution Approach 1:
The patent implements a clocking scheme where input sampling switches are toggled at half the frequency of internal sampling switches. Specifically, the first and second input sampling switches are controlled by a first clock signal with frequency f_clk/2, while the third and fourth input sampling switches are controlled by a second clock signal with frequency f_clk. This periodic switching pattern maintains sampling accuracy while reducing charge loss by half compared to switching all switches at full clock frequency.
2Productivity
If switching frequency is increased, then sampling rate is improved, but distortion performance deteriorates due to higher switching activity
Solution Approach 1:
The patent employs differential switching patterns where input sampling switches operate at half frequency (f_clk/2) and internal sampling switches operate at full frequency (f_clk). This creates a periodic pattern where switching activity is distributed across different phases, reducing simultaneous switching noise and distortion while maintaining the overall sampling rate. The alternating clock phases ensure that not all switches change state at the same time, thereby reducing harmonic distortion.
3Loss of energy
If power efficiency is improved by reducing switching frequency, then charge loss decreases, but equivalent input impedance decreases
Solution Approach 1:
The patent changes the switching frequency parameter for different switch sets to resolve the contradiction. By setting input sampling switches to f_clk/2 and internal sampling switches to f_clk, the system achieves a balance where power efficiency is improved (compared to all switches at f_clk) while maintaining adequate input impedance through the differential switching action that effectively doubles the equivalent input impedance.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.