Decision Feedback Equalizer Circuit for Minimum ISI Correction Delay
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Solution Overview
Problem
Decision feedback equalizers in serial transmission systems face challenges in reducing correction delay and achieving sufficient ISI compensation, particularly at higher frequencies, due to limitations in linear equalizer capabilities and timing constraints in clock recovery.
Innovation Solution
A decision feedback equalizer architecture that includes a multiplexer controlled by a clock signal to generate digital levels for correction coefficients, paired with latches and additional multiplexers to reduce propagation delay and improve sensitivity, allowing for correction based on multiple preceding bits, and error evaluation using variable-threshold samplers and logic circuits to adapt coefficients and thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decision feedback equalization is implemented to compensate for channel degradation, then signal recovery quality is improved, but correction delay increases due to the processing time required for ISI cancellation
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing correction values in lookup tables before they are needed during signal processing. The equalizer coefficients and ISI correction values are calculated in advance based on channel characteristics, allowing the equalizer to apply corrections without real-time computation delay, thus resolving the contradiction between maintaining high signal recovery quality and minimizing correction delay
Solution Approach 2:
The patent segments the equalization process into distinct functional blocks: a linear equalizer for initial signal conditioning, followed by a decision feedback equalizer for ISI cancellation. This segmentation allows each block to be optimized independently, with the LWE handling frequency-dependent losses and the DFE handling inter-symbol interference, thereby achieving effective signal recovery while managing overall processing delay through parallel operation of these segmented components
2Measurement precision
If multiple correction coefficients are used to improve ISI deletion accuracy, then measurement precision is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent merges multiple correction coefficient functions into a unified decision feedback equalizer structure that shares common circuit resources. The DFE uses a single feedback path that processes multiple previous bit decisions through tapped delay lines, combining the functionality of multiple coefficients into one integrated circuit block rather than requiring separate correction circuits for each coefficient, thus achieving high ISI deletion accuracy while controlling circuit complexity
Solution Approach 2:
The patent uses lookup tables to store pre-computed correction values for multiple coefficients, creating tabular copies of the correction data that can be quickly accessed during equalization. This approach allows the system to implement multiple correction coefficients with high precision by storing their values in memory structures rather than implementing complex real-time computation circuits for each coefficient, thereby achieving high measurement precision with reduced device complexity
Data Source
AI summary
A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.