Differential Sampling Circuit Harmonic Cancellation for Higher SFDR
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face a challenge in achieving high Spurious-Free Dynamic Range (SFDR) due to harmonic content generated by phase imbalance in differential sampling circuits, primarily caused by non-linearity in MOS sampling switches and junction diodes, which results in dominant second and third harmonic components at high input frequencies.
Innovation Solution
A compensation circuit is introduced, utilizing field-effect transistors operating in saturation mode in parallel with the differential switch of the sampling circuit, which redirects harmonic content away from sampling capacitors and through the compensation circuit, effectively cancelling second harmonic currents and reducing third harmonic content by using transistors of equal width and length to the differential switch, coupled with current sources to maintain saturation region operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOS sampling switches and junction diodes are used in differential sampling circuits, then the ADC can operate at high input frequencies, but harmonic content is generated due to non-linearity, reducing SFDR
Solution Approach 1:
The patent utilizes the non-linear characteristics of MOS transistors operating in saturation mode to generate harmonic content that is equal and opposite to the harmonic content generated by the differential sampling switches. By carefully designing the compensation circuit with transistors of equal width and length, the harmful second harmonic distortion is converted into a beneficial canceling signal, achieving harmonic cancellation without sacrificing high-frequency operation capability
Solution Approach 2:
The patent introduces asymmetry by adding a compensation circuit that is structurally different from the main differential sampling path. The compensation circuit uses transistors configured in saturation mode with specific width and length parameters that differ from the linear-mode differential switches, creating an asymmetric structure that generates opposing harmonic content for cancellation purposes
2Measurement precision
If a compensation circuit is added to cancel harmonic content, then SFDR is improved, but device complexity increases
Solution Approach 1:
The patent segments the harmonic cancellation function into a separate compensation circuit that operates independently from the main differential sampling path. This segmentation allows the compensation circuit to be designed and optimized separately, using transistors of equal width and length configured in saturation mode, while maintaining clear functional separation from the linear-mode differential switches, thus managing complexity through functional decomposition
Solution Approach 2:
The patent achieves harmonic cancellation by changing the operating parameters of the compensation transistors, specifically setting them to operate in saturation mode with equal width and length parameters. This parameter optimization allows the compensation circuit to generate precise harmonic content for cancellation while maintaining a compact design that minimizes the increase in device complexity
Data Source
AI summary
A compensation circuit for eliminating harmonic content resulting from a phase imbalance in a differential sampling circuit. The compensation circuit includes a pair of field effect transistors operating in saturation mode, each field effect transistor coupled in parallel with the differential switch of the sampling circuit, which operates in linear mode. The saturation region transistors across the differential switch allow the harmonic content to flow through the compensation circuit instead of the sampling capacitors of the sampling circuit.