Differential CDS Switched-Capacitor Integrator With Parasitic Cancellation
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Solution Overview
Problem
Existing switched-capacitor gain circuits face limitations due to flicker noise, finite amplifier gain, and DC offsets, which affect accuracy, and correlated double sampling techniques introduce integrator leakage that limits ADC resolution, especially in first-order sigma delta converters.
Innovation Solution
A differential CDS switched capacitor integrator circuit is designed with dummy capacitive elements that track and cancel parasitic capacitance, using MOSFETs to emulate and compensate for the parasitic capacitance of integration switches, thereby improving signal accuracy and reducing leakage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If correlated double sampling is used to compensate for offset and improve accuracy, then measurement precision is improved, but integrator leakage increases due to parasitic capacitance
Solution Approach 1:
The patent converts the harmful parasitic capacitance into a beneficial element by deliberately adding dummy capacitors that match the parasitic values. These dummy capacitors are used to pre-charge or pre-discharge the integration capacitor, thereby compensating for the charge loss that would otherwise occur due to parasitic effects during switching transitions.
Solution Approach 2:
The patent changes the electrical parameters of the circuit by adding controlled capacitance values through dummy capacitors. By carefully selecting the capacitance values to match the parasitic capacitance, the circuit parameters are adjusted to achieve charge compensation and eliminate the adverse effects of parasitic elements on integration accuracy.
2Measurement precision
If additional capacitors are added to compensate for parasitic capacitance, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent creates simplified copies of the parasitic capacitance effects using dummy capacitors. Instead of trying to eliminate or complexly model the parasitic elements, the invention copies their capacitive effect and uses this copy to compensate for the harmful charge redistribution, thereby simplifying the overall compensation approach.
Solution Approach 2:
The dummy capacitors serve multiple functions: they compensate for parasitic capacitance effects, maintain charge balance during switching, and improve integration accuracy. This multi-functionality reduces the need for additional complex compensation circuits, thereby limiting the increase in device complexity.
3Measurement precision
If larger integration capacitor is used to reduce leakage effects, then measurement precision is improved, but area of the circuit increases
Solution Approach 1:
The patent changes the charge management approach by introducing controlled charge compensation through dummy capacitors. This allows the use of smaller integration capacitors while maintaining accuracy, as the charge loss from parasitic effects is compensated rather than relying solely on larger capacitance values to minimize the impact.
Solution Approach 2:
The patent converts the harmful parasitic capacitance into a beneficial compensation mechanism. By using dummy capacitors to match and counteract the parasitic effects, the circuit can achieve high precision with smaller integration capacitors, thereby reducing the overall circuit area while maintaining or improving measurement accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the accuracy of ADCs by compensating for parasitic capacitance, reducing charge loss, and improving the linearity and resolution of analog-to-digital converters beyond the 16-bit limit, while maintaining circuit simplicity and avoiding bandwidth constraints.
Implementation Method 1
Parasitic capacitances of the prior art integration switches may cause leaky integrators that limit the maximum achievable resolution of Analog-to-Digital Converters (ADCs)
Data Source
AI summary
Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.