Switched Capacitor Switch Topology for Low Charge Injection
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Solution Overview
Problem
Switched capacitor circuits in integrated circuits face limitations due to charge injection and clock feed-through mechanisms, which introduce errors and are challenging to compensate for effectively in existing technologies, particularly due to the need for component matching and increased power dissipation.
Innovation Solution
A low charge injection, low clock feed-through switch design that uses a second 'coarse' transistor switch in parallel with the main switch, with clock signals of different durations to reduce the physical size of the main switch and minimize errors, allowing for reduced charge injection and clock feed-through without relying on component matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor switch is used in switched capacitor circuits, then the circuit structure is simple, but charge injection and clock feed-through errors are significant
Solution Approach 1:
The single MOS transistor switch is segmented into two parallel switches: a main switch and a coarse switch. The main switch has optimized dimensions for low charge injection, while the coarse switch handles the bulk of the switching function. This segmentation allows each switch to be optimized for its specific function, reducing overall charge injection and clock feed-through errors while maintaining circuit functionality.
2Object-generated harmful factors
If the main switch is made smaller to reduce charge injection, then charge injection is reduced, but the switch resistance increases and settling time increases
Solution Approach 1:
The switching function is divided between two parallel switches with different characteristics. The main switch is sized for low charge injection with optimized W/L ratio, while the coarse switch provides low resistance path during the coarse integration phase. This segmentation allows the main switch to be small without excessive resistance penalty since the coarse switch compensates for the resistance increase.
Solution Approach 2:
The circuit uses different clock signal parameters (duration and timing) for the main switch and coarse switch. The coarse switch operates during a longer coarse integration phase with clock signal Pcoarse, while the main switch operates during a shorter fine integration phase with clock signal P. This parameter differentiation allows optimization of each switch's operating conditions to minimize both charge injection and settling time.
3Object-generated harmful factors
If known charge injection compensation schemes are used, then charge injection is compensated, but component matching requirements increase and power dissipation increases
Solution Approach 1:
Instead of compensating for charge injection after it occurs, the circuit preliminarily prevents charge injection by using a main switch with optimized dimensions and operating conditions. The main switch is designed from the outset to minimize charge injection through careful selection of W/L ratio and operating phase, eliminating the need for complex compensation circuits and component matching.
Solution Approach 2:
The charge injection problem is extracted and handled separately by the coarse switch, which operates during a dedicated coarse integration phase. By separating the switching functions into coarse and fine phases with different switches, the charge injection from each switch can be independently managed, reducing the need for precise component matching between multiple compensating elements.
4Speed
If the main switch is made larger to reduce resistance, then switch resistance is reduced, but charge injection and clock feed-through increase
Solution Approach 1:
The switching function is segmented into two parallel paths: one through the main switch optimized for low charge injection, and another through the coarse switch that handles the bulk current. This segmentation allows the main switch to maintain small dimensions for low charge injection while the coarse switch provides the low resistance path needed for fast switching, eliminating the trade-off between size and charge injection.
Data Source
AI summary
A low charge injection, low clock feed-through switch (1) has an input signal (Vin) applied both to the sources of first (S1) and second (2) switching transistors. A first clock signal (P) having pulses of a first duration ts is applied to a gate of the first switching transistor, and a second clock signal (Pcoarse) having pulses of a second duration m×ts substantially less than the first duration is applied to a gate of the second switching transistor. A capacitor (C) is charged toward the input voltage through both the first and second switching transistors during the pulse of the second clock signal. The capacitor is charged further toward the input voltage during a remaining portion of the pulse of the first clock signal.