Switched Capacitor Comparator Shorting Scheme for Settling Error Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing offset compensated comparators in analog to digital converters face challenges in reducing built-in offset voltages and settling errors due to differences in impedance between reference voltage sources, leading to transient errors during the comparison phase.
Innovation Solution
The implementation of a low offset switched capacitor comparator system that operates in two phases: sampling the input voltage and reference voltage, and shorting the differential outputs of the amplifier during a settling period to reduce transient settling errors, allowing for automatic cancellation of comparator input offset voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If offset cancellation is performed by connecting comparators to driving amplifier through series switches, then comparator offset is reduced, but transient settling errors occur due to impedance differences between reference voltage sources
Solution Approach 1:
The patent applies preliminary action by performing offset cancellation in a first phase before the comparison phase. During this first phase, switches connect the comparator inputs to the driving amplifier outputs, allowing offset voltages to be stored on capacitors. This preliminary offset cancellation prevents the harmful effect of offset during the subsequent comparison phase, while the timing separation avoids the transient settling errors that would occur if offset cancellation and comparison happened simultaneously.
Solution Approach 2:
The patent implements periodic action through phased operation with clock signals. The system alternates between a first phase (offset cancellation) and a second phase (comparison), controlled by non-overlapping clock signals. This periodic switching allows the system to achieve both offset reduction and accurate comparison by separating these functions in time, eliminating the transient settling errors that would occur in continuous operation.
2Device complexity
If reference voltage VREFP is generated from buffer circuit and VREFM connected directly to ground, then reference voltage generation is simplified, but AC settling times differ causing transient errors
Solution Approach 1:
The patent uses preliminary action by dedicating a specific first phase for offset cancellation and capacitor charging before the comparison phase. During this first phase, both reference voltages (VREFP and VREFM) have sufficient time to settle onto their respective capacitors without the pressure of simultaneous comparison. This timing separation ensures that even with different impedance sources, both references are fully settled before the comparison phase begins, eliminating transient errors while maintaining the simple reference generation architecture.
3Measurement precision
If comparator inputs are shorted during offset cancellation phase, then offset is stored in capacitors, but settling errors occur during the transition to comparison phase
Solution Approach 1:
The patent applies periodic action through clearly defined phases controlled by clock signals. The first phase (Φ1) is dedicated to offset cancellation with inputs shorted, allowing sufficient time for capacitors to charge. The second phase (Φ2) is dedicated to comparison with inputs disconnected. This periodic separation ensures that the settling time required for offset cancellation is fully provided during Φ1, eliminating the need for additional settling time during the transition to comparison, thus reducing overall loss of time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces settling errors and allows for precise comparison by using a clocked comparator with a switched capacitor input stage and differential outputs, enabling efficient rejection of power supply noise and arbitrary scaling between reference and input voltages.
Implementation Method 1
a switched capacitor input stage
Implementation Method 2
a switch electrically connected across the differential outputs of the clocked amplifier and across the inputs to the clocked comparator, the switch configured to short the inputs of the clocked comparator during a settling period
Data Source
AI summary
The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.