Differential Sensor Integration Circuit for Noise and Pulse Overlap
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Solution Overview
Problem
Traditional touch panel sample and hold (S/H) circuits face saturation issues due to instantaneous noise and pulse overlap problems, particularly in high-frequency applications, leading to reduced measurement accuracy and increased operation time.
Innovation Solution
A multi-stage S/H circuit design that integrates both positive and negative pulse cycles, using Stage 1 and Stage 2 integration circuits to concurrently process differential signals, thereby reducing noise saturation and pulse overlap, and sharing capacitors with SAR-ADC to optimize die area and manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional S/H circuits operate only in positive or negative pulses, then circuit complexity is reduced, but 50% of clock cycles are wasted and productivity decreases
Solution Approach 1:
The patent divides the S/H circuit into two separate stages: a first S/H circuit for positive pulses and a second S/H circuit for negative pulses. Each stage operates independently during its respective pulse type, eliminating the need for complex inverter circuits while fully utilizing both positive and negative clock cycles. This segmentation resolves the contradiction by simplifying individual circuit blocks while achieving complete clock cycle utilization at the system level.
Solution Approach 2:
The patent implements periodic switching between the first and second S/H circuits based on the clock signal polarity. The first circuit operates during positive pulses while the second operates during negative pulses, creating a periodic alternation that fully utilizes both halves of the clock cycle. This periodic action doubles the effective productivity compared to single-polarity operation without increasing overall system complexity.
2Productivity
If inverters are used to enable operation in both positive and negative pulses, then productivity improves, but transmission time delays cause pulse overlap and reliability deteriorates
Solution Approach 1:
Instead of using a single S/H circuit with an inverter, the patent segments the processing into two dedicated circuits: one for positive pulses and one for negative pulses. This eliminates the inverter component entirely, removing the source of transmission time delays and pulse overlap. Each circuit maintains precise timing for its designated pulse type without interference from inversion delays.
Solution Approach 2:
The patent introduces a clock signal routing mechanism that acts as an intermediary, directing positive pulses to the first S/H circuit and negative pulses to the second S/H circuit. This intermediary routing eliminates the need for signal inversion while still enabling both circuits to operate at full capacity, thereby maintaining pulse timing accuracy while improving productivity.
3Measurement precision
If capacitor size is increased to reduce noise saturation, then measurement precision improves, but die area increases and manufacturing cost rises
Solution Approach 1:
The patent segments the capacitor requirements into two separate, smaller capacitors—one for the first S/H circuit and one for the second S/H circuit. Each capacitor only needs to handle half of the total signal load (positive or negative pulses), allowing them to be smaller than a single large capacitor would need to be. The combined noise resistance of the two smaller capacitors equals or exceeds that of one large capacitor while occupying less total die area.
Solution Approach 2:
Each S/H circuit performs partial integration of the total signal spectrum (only positive or only negative pulses), which allows the use of smaller capacitors that would be insufficient for full-signal handling. This partial action approach maintains adequate noise resistance for each channel while reducing the total capacitor size and die area required compared to a single circuit handling all pulses.
4Measurement precision
If multi-stage integration is implemented to process differential signals, then measurement precision and noise resistance improve, but device complexity increases
Solution Approach 1:
The patent implements a two-stage integration architecture where the first stage processes positive pulses and the second stage processes negative pulses. Each stage is relatively simple in design, but together they achieve differential signal processing with improved measurement precision. The segmentation into two dedicated stages avoids the complexity of a single complex stage while maintaining high accuracy through complementary operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively alleviates noise saturation and pulse overlap issues, improving measurement accuracy and reducing operation time while minimizing die area and manufacturing costs by concurrently processing differential signals across multiple stages.
Implementation Method 1
Each of the Stage 1 integration circuits is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal that is reverse to the Stage 1 positive signal
Data Source
AI summary
The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuits arranged in an array and a plurality of Stage 2 integration circuits arranged in an array. Each of the Stage 1 integration circuits is configured to concurrently integrate an input signal, and to send out a Stage 1 positive signal and a Stage 1 negative signal that is reverse to the Stage 1 positive signal. Each of the Stage 2 integration circuits is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to the corresponding Stage 1 integration circuit to output a Stage 2 signal.