High-Side NMOS Switch Control With Slew-Rate Feedback
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Solution Overview
Problem
High-side NMOS switches require charge pumps to drive the gate terminal above the positive voltage rail, leading to increased costs and design complexities, and existing inrush current control methods using PMOS switches result in high inrush currents due to steep turn-on transitions.
Innovation Solution
A circuit arrangement with voltage and current provisioning means, a control stage, and feedback control links to limit the slew rate of NMOS power switches, allowing for reduced charge pump usage and zero current draw during steady state, using a single charge pump for an array of switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If enhancement type NMOS switches are used as high-side switches, then the drain to source resistance is reduced and parasitic body diodes are simplified, but charge pumps are required to bias the gate terminal above the positive voltage rail
Solution Approach 1:
The charge pump circuit is designed to serve multiple NMOS switches simultaneously, with each switch driver cell sharing the charge pump resource. This multi-functional approach reduces the total number of charge pumps needed in the system while maintaining the ability to drive multiple high-side NMOS switches above the positive voltage rail.
Solution Approach 2:
The gate bias voltage is generated locally at each switch driver cell using a shared charge pump, eliminating the need for external bias voltage sources. The driver circuit autonomously generates the required gate voltage to drive the NMOS switch above the positive rail, making the system self-sufficient.
2Device complexity
If PMOS switches are used to avoid charge pumps, then charge pump complexity is reduced, but the drain to source resistance increases and parasitic body diodes become problematic
Solution Approach 1:
The invention changes the operating parameters of NMOS switches by generating a gate voltage that exceeds the positive supply voltage (VDD). This parameter change enables NMOS switches to function as high-side switches with low on-resistance, overcoming the traditional limitation that NMOS requires gate voltage above the source voltage, which would otherwise require the source to be at a lower potential.
3Object-affected harmful factors
If a two-phase approach with two parallel PMOS switches is used for inrush current control, then initial inrush current is limited, but high resistive load conditions cause delayed voltage rise and subsequent high inrush current during the second phase
Solution Approach 1:
A feedback control link is implemented that monitors the output voltage of the NMOS switch and regulates the current supplied to the load. This feedback mechanism ensures that the output voltage rises at a controlled rate regardless of load conditions, preventing the delayed voltage rise problem that occurs with resistive loads in two-phase PMOS approaches.
Solution Approach 2:
The switch driver circuit dynamically adjusts its operation based on real-time conditions. During the turn-on transition, the circuit actively controls the rate of voltage rise at the output, adapting to varying load conditions including high resistive loads, ensuring consistent inrush current limitation without the delays characteristic of static two-phase approaches.
4Ease of operation
If multiple charge pumps are used for an array of NMOS switches, then each switch can be independently controlled, but the number of charge pumps and current draw during steady state operation increases
Solution Approach 1:
The charge pump circuit is designed to serve multiple NMOS switches simultaneously, with each switch driver cell sharing the charge pump resource. This multi-functional approach reduces the total number of charge pumps needed in the system while maintaining the ability to drive multiple high-side NMOS switches above the positive voltage rail.
Solution Approach 2:
The charge pump operates in a periodic manner, activating only during the transition periods when switches need to change state. During steady-state operation when switches are already in their required states, the charge pump can be deactivated or operated at reduced capacity, minimizing current draw while maintaining switch control capability when needed.
Data Source
AI summary
A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.