Anti-Fuse Memory Cell Layout With Shared Varactor N-Well
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Solution Overview
Problem
Anti-fuse memory cells in prior art suffer from large area requirements, high on-resistance, and low reading speed and reliability, particularly in advanced semiconductor technologies.
Innovation Solution
An anti-fuse memory cell design incorporating a PMOS transistor and a varactor within an N-well region, where the varactor serves as both a low-voltage process device and an N-well tap for the PMOS transistor, sharing a gate and utilizing a controllable power supply with programmed high voltage for programming and normal operating voltage for reading, thereby reducing area and improving reliability and reading speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional anti-fuse memory cell structure is used, then the memory can be implemented, but the area occupied by each memory cell is large
Solution Approach 1:
The patent merges the N-well tap function into the varactor structure by sharing the N-well region between the PMOS transistor and the varactor. This integration eliminates the need for separate N-well tap structures, reducing the overall memory cell area while maintaining proper N-well potential control for reliable operation
Solution Approach 2:
The varactor structure serves multiple functions simultaneously: it acts as the storage element for anti-fuse programming, provides N-well potential control through shared N-well region, and enables compact layout. This multi-functionality reduces the number of separate components needed, thereby reducing area
2Reliability
If a conventional anti-fuse memory cell structure is used, then the memory can be implemented, but the on-resistance is high
Solution Approach 1:
By merging the N-well tap function into the varactor structure through shared N-well region, the patent reduces the number of interfaces and connections needed. This integration lowers the overall on-resistance by eliminating series resistance contributions from separate tap structures and reducing parasitic effects
3Speed
If a conventional anti-fuse memory cell structure is used, then the memory can be implemented, but the reading speed is low
Solution Approach 1:
The integrated structure with shared N-well region reduces parasitic capacitance and resistance, enabling faster charge/discharge cycles during read operations. The compact design allows for smaller feature sizes and faster signal propagation, improving reading speed while maintaining reliability through proper N-well potential control
4Reliability
If separate N-well tap structures are used for PMOS transistor, then the N-well potential can be controlled, but the chip area increases
Solution Approach 1:
The patent merges the N-well tap function into the varactor structure by having both the PMOS transistor and varactor share the same N-well region. This integration eliminates the need for separate N-well tap structures, reducing chip area while maintaining proper N-well potential control through the shared N-well connection
Solution Approach 2:
The shared N-well region serves dual purposes: it provides the N-well potential control needed for PMOS transistor operation and simultaneously serves as the foundation for the varactor structure. This multi-functionality eliminates redundant structures and reduces overall chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability and reading speed of anti-fuse memory cells by reducing on-resistance and area usage, simplifying the comparator design, and being compatible with existing CMOS manufacturing processes without additional masks or processes, thus improving chip yield and reducing costs.
Implementation Method 1
a varactor... the gate of the PMOS transistor and a gate of the varactor are both connected to a drain of the first NMOS transistor
Data Source
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AI summary
Disclosed are an anti-fuse memory cell and a data read-write circuit thereof. The anti-fuse memory cell comprises a base, the base is provided with an N-well and a non-N-well region; the non-N-well region is provided with a first NMOS transistor; a gate of the first NMOS transistor is used for inputting a first selection signal; the N-well is provided with a PMOS transistor and a varactor; a gate of the PMOS transistor and a gate of the varactor are both connected to a drain of the first NMOS transistor; and a drain, a source and a substrate of the PMOS transistor and a drain, a source, and a substrate of the varactor are all connected to a controllable power supply. In the invention, an area of a programmable region is increased, an on resistance of the memory cell after breakdown is reduced, a reliability is improved, a cost is reduced, and a data reading speed is increased.