Anti-Fuse Array ECC Decoder for Fuse Data Error Correction
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Solution Overview
Problem
Semiconductor memory devices face reliability issues due to malfunctions in anti-fuse elements during operations, which can lead to errors in fuse data used for identifying and replacing defective memory cells.
Innovation Solution
Incorporating a second anti-fuse array to store error correction code (ECC) data associated with first fuse data, and an ECC decoder to generate error-free second fuse data by correcting errors in the first fuse data, thereby improving the reliability of redundancy operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse elements are used to store fuse data for identifying defective memory cells, then the memory device can perform redundancy operations to replace defective cells, but the anti-fuse elements may malfunction during operation causing errors in fuse data
Solution Approach 1:
An ECC decoder is introduced as an intermediary component between the anti-fuse elements and the redundancy operation logic. The ECC decoder reads the fuse data from anti-fuse elements, corrects any errors using ECC algorithms, and provides corrected data to the redundancy operation logic. This intermediary mechanism protects the system from harmful malfunctions in anti-fuse elements while maintaining the ability to perform redundancy operations.
Solution Approach 2:
The ECC decoder implements a feedback mechanism where it continuously monitors the integrity of fuse data stored in anti-fuse elements and automatically corrects detected errors. The correction process uses feedback from the ECC check bits to modify the data bits, ensuring that even if anti-fuse elements malfunction, the corrected fuse data remains accurate for reliable redundancy operations.
2Reliability
If error correction code (ECC) data is stored in a second anti-fuse array to correct errors in first fuse data, then the reliability of fuse data is improved, but the device complexity increases due to additional anti-fuse array and ECC decoder
Solution Approach 1:
The fuse data storage system is segmented into two separate anti-fuse arrays: one for storing data bits and another for storing ECC check bits. This segmentation allows independent optimization of each array and enables parallel processing during ECC verification. The ECC decoder is also segmented into separate logic blocks for syndrome calculation and bit flipping, making the complex correction process more manageable and modular.
Solution Approach 2:
The second anti-fuse array serving ECC storage is integrated into the existing anti-fuse box structure, sharing common control logic and read circuitry with the first anti-fuse array. The ECC decoder is designed to work with both types of anti-fuse arrays using unified control signals and data paths. This multi-functionality approach reduces overall device complexity by eliminating redundant components while maintaining error correction capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of fuse data used in semiconductor memory devices by correcting errors and ensuring accurate replacement of defective memory cells, improving the overall efficiency and reliability of read and write operations.
Implementation Method 1
A voltage difference between terminals of the anti-fuse element may be used to destroy the insulating material causing the two electrodes to short-circuit. A voltage that destroys the insulating material of the anti-fuse element is referred to as a programming voltage.
Data Source
AI summary
A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.