Anti-Fuse Gate Oxide Breakdown Leakage Current Control

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Solution Overview

Problem

In semiconductor devices, the breakdown of the gate oxide layer in MOSFET anti-fuse circuits leads to leakage currents, degrading device operation and varying current flow based on the position of the broken point, which affects the reliability and efficiency of the anti-fuse circuit.

Innovation Solution

The anti-fuse circuit is designed with a semiconductor substrate, isolation region, channel diffusion region, gate oxide layer, and gate electrode, where the channel diffusion region has a conductivity type opposite to the substrate, reducing parasitic currents by forming an ohmic contact between the gate electrode and the substrate after the gate oxide layer breaks, and the drain and source regions have higher impurity concentrations to control current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a MOSFET with a thin gate oxide layer is used for an anti-fuse, then the anti-fuse can be turned on when conditions are satisfied, but a leakage current flows through the semiconductor substrate when the gate oxide layer breaks, degrading device operation

Engineering Contradiction:
Improvedevice operationVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The semiconductor substrate is segmented into multiple regions with different conductivity types. A first conductivity type region is created at a first depth from the top surface, and a second conductivity type region is created at a second depth (deeper than the first). This segmentation isolates the breakdown path from the substrate bulk, preventing leakage current from flowing through the entire substrate while maintaining the anti-fuse functionality.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the gate oxide layer breaks at different positions, then the anti-fuse activates, but the leakage current varies depending on the position of the broken point, affecting reliability

Engineering Contradiction:
Improveoperation consistencyVSAvoidleakage current variation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Different regions of the semiconductor substrate are assigned different conductivity types at different depths. The first conductivity type region is located at a shallower depth while the second conductivity type region is located at a deeper depth. This creates localized electrical properties that guide the breakdown current through a controlled path, ensuring consistent electrical characteristics regardless of where the gate oxide layer breaks.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design stabilizes current flow and reduces leakage currents, providing predictable dispersion characteristics and improved reliability by minimizing parasitic currents through the substrate, even when the gate oxide layer breaks at different points, ensuring consistent operation.

Implementation Method 1

the gate oxide layer is configured to break, forming an ohmic contact between the gate electrode and the substrate

Methodology Applied
Scientific EffectBreakdown of gate oxide layer: Avalanche Breakdown

Implementation Method 2

The channel diffusion region has a second conductivity type opposite to the first conductivity type... reduce a leakage current flowing through a bulk

Methodology Applied
Scientific EffectConductivity type blocking: Electrical Resistance

Data Source

PatentUS8514648B2Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
Publication Date: 2013.08.20 SAMSUNG ELECTRONICS CO LTD
  • US8514648B2 patent drawing
  • US8514648B2 patent drawing
  • US8514648B2 patent drawing

AI summary

Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.