Antifuse Memory Arrays for Simultaneous Data Zeroization
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Solution Overview
Problem
Existing one-time programmable (OTP) read-only memory (ROM) technologies face challenges in efficiently deleting or erasing data, particularly when sensitive information or security concerns are involved, as ROM is designed to be non-overwritable, and existing zeroization methods like efuse implementations are complex and require pre-reading to identify bits for switching.
Innovation Solution
Implementing memory cells with antifuse technology using a transistor with a thin gate oxide that undergoes dielectric breakdown to switch from an open to a closed circuit, allowing for simultaneous zeroization of all memory cells without pre-reading, thereby simplifying the process and enabling higher density memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional efuse zeroization methods are used, then data deletion can be achieved, but the process becomes complex and requires pre-reading to identify bits for switching
Solution Approach 1:
Instead of switching bits from 0 to 1 as in traditional efuse methods, the invention inverts the approach by switching all bits from 1 to 0 simultaneously. This inversion eliminates the need for pre-reading and identifying specific bits, thereby simplifying the zeroization process while maintaining security.
Solution Approach 2:
The antifuse technology enables the memory cells to self-zeroize without external intervention to identify which bits need switching. The simultaneous switching of all bits to 0 is achieved through the antifuse mechanism itself, eliminating the need for complex pre-reading and selection processes.
2Reliability
If OTP ROM is designed to be non-overwritable, then data security is improved, but data deletion becomes difficult
Solution Approach 1:
The invention changes the physical state parameter of the memory cells by using antifuse technology that allows permanent modification from 1 to 0. This parameter change enables secure data deletion while maintaining the non-overwritable characteristic of OTP ROM, as the changes are permanent and cannot be reversed.
Solution Approach 2:
The invention converts the harmful limitation of OTP ROM (non-overwritable property) into a benefit by using the antifuse mechanism to permanently set bits to 0. The permanent nature of the change provides both security (cannot be overwritten) and deletability (can be permanently zeroized), resolving the contradiction between these two requirements.
3Productivity
If existing zeroization methods are used, then data can be deleted, but yield loss increases and device size increases
Solution Approach 1:
The invention merges the zeroization operation with the existing memory cell structure by integrating antifuse technology directly into the OTP ROM cells. This merging eliminates the need for separate, complex zeroization circuits and processes, thereby reducing yield loss and device size while maintaining efficient zeroization capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The antifuse technology enables efficient and secure deletion of data by switching all bits to a predetermined value, reducing yield loss, complexity, and size, while being resistant to reverse-engineering, thus supporting high-density, reliable, and affordable information storage.
Implementation Method 1
a transistor with a thin gate oxide that undergoes dielectric breakdown to switch from an open to a closed circuit
Data Source
AI summary
Methods and apparatus to delete and prevent recovery of data stored in a memory array are disclosed. An example apparatus includes machine readable instructions; and at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to: obtain an instruction to zeroize a memory array; and cause a voltage to be applied across a plurality of transistors associated with a plurality of memory cells in the memory array. The voltage is to set the plurality of memory cells to a same logical value. The voltage is applied across the transistors regardless of the logical values of the plurality of memory cells prior to receiving the instruction to zeroize the memory array.