Anti-Fuse Memory Structure Nested in CMOS Isolation
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Solution Overview
Problem
Nonvolatile memory devices face challenges in manufacturing complexity and increased chip size due to different manufacturing techniques from standard logic processes, and existing designs often lack efficient methods to reduce device size while maintaining functionality.
Innovation Solution
A memory device design featuring a semiconductor substrate with an isolation structure and an anti-fuse structure, where electrodes are disposed within the isolation structure, allowing for a compact configuration and simplified manufacturing process, and programming is achieved by applying voltages to convert the isolation structure into a permanent conductive path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile memory devices use different manufacturing techniques from standard logic processes, then data storage functionality is achieved, but manufacturing complexity and chip size increase
Solution Approach 1:
The anti-fuse structure is integrated within the standard CMOS isolation region, allowing the same isolation structure to serve dual purposes: electrical isolation for logic circuits and housing for the anti-fuse memory element. This eliminates the need for separate dedicated memory manufacturing processes while maintaining nonvolatile data storage functionality.
Solution Approach 2:
The patent combines the anti-fuse memory structure with the standard CMOS isolation structure, merging two previously separate components into a unified structure. The anti-fuse electrodes and dielectric are integrated within the isolation region, reducing overall device complexity and enabling standard logic process manufacturing.
2Reliability
If nonvolatile memory devices use different manufacturing techniques from standard logic processes, then data storage functionality is achieved, but chip size increases
Solution Approach 1:
The anti-fuse structure is nested within the existing isolation region of the CMOS device. The first and second electrodes are positioned within the isolation structure, with the anti-fuse dielectric material filling the space between them, effectively utilizing the isolation region volume for dual purposes and minimizing additional chip area.
3Area of stationary object
If electrodes are positioned with top surfaces below the semiconductor substrate top surface, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The anti-fuse dielectric material is deposited to fill the space between the electrodes before the electrodes are fully formed or planarized. This preliminary filling action ensures that the electrodes are automatically positioned at the correct depth relative to the substrate surface, reducing the need for high-precision post-forming adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces the size of the memory device and simplifies the manufacturing process, while maintaining effective data storage capabilities through the anti-fuse structure's conductive path formation.
Implementation Method 1
a first voltage is applied to the first electrode and a second voltage different from the first voltage is applied to the second electrode to convert a portion of the isolation structure between the first electrode and the second electrode into a permanent electrically conductive path
Data Source
AI summary
A memory device includes a semiconductor substrate, an isolation structure, and an anti-fuse structure. The isolation structure is disposed in the semiconductor substrate. The anti-fuse structure is disposed in the isolation structure and includes a first electrode and a second electrode. The second electrode is disposed adjacent to the first electrode. Both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate.